[AArch64] Make register indices be full 64-bit values

aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked.  This meant large invalid indices could be silently
truncated to smaller valid indices.

The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index.  I went for the latter for two
reasons:

      - Doing the range checking in operand_general_constraint_met_p
        seems structurally cleaner than doing it while parsing.

      - The bitfields didn't really buy us anything.  The imm field
        of the union is already 128 bits, so we can use a full int64_t
        index without growing the structure.

The patch also adds missing range checks for the elements in a register
list index.

include/
	* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.

opcodes/
	* aarch64-opc.c (operand_general_constraint_met_p): Check the
	range of ldst_elemlist operands.
	(print_register_list): Use PRIi64 to print the index.
	(aarch64_print_operand): Likewise.

gas/
	* testsuite/gas/aarch64/diagnostic.s,
	testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.

1 files changed, 3 insertions, 3 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e6f080c..b35a818 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -748,8 +748,8 @@ struct aarch64_opnd_info
 	} reg;
       struct
 	{
-	  unsigned regno : 5;
-	  unsigned index : 4;
+	  unsigned int regno;
+	  int64_t index;
 	} reglane;
       /* e.g. LVn.  */
       struct
@@ -759,7 +759,7 @@ struct aarch64_opnd_info
 	  /* 1 if it is a list of reg element.  */
 	  unsigned has_index : 1;
 	  /* Lane index; valid only when has_index is 1.  */
-	  unsigned index : 4;
+	  int64_t index;
 	} reglist;
       /* e.g. immediate or pc relative address offset.  */
       struct