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authorMatthew Wahab <matthew.wahab@arm.com>2015-12-14 17:27:52 +0000
committerMatthew Wahab <matthew.wahab@arm.com>2015-12-14 17:27:52 +0000
commit3067d3b96cfb88e86acf94d2aa1575cff0e0110f (patch)
tree0c6cc9bfde55f4e41729af9bc006f6579a103738 /include/opcode/aarch64.h
parent65f2205d609d9c38e1a7f009d2c6833aecfb83eb (diff)
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[AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type, 2H. This patch adds support for this vector type to binutils. The patch adds a new operand qualifier to the enum aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation used by aarch64-dis.c:get_vreg_qualifier_from_value, called when decoding an instruction. Since the new vector type is only used in FP16 scalar pairwise instructions which do not require the function, this patch adjusts the function to ignore the new qualifier. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to take into account new vector type 2H. (vectype_to_qualifier): Likewise. include/opcode/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (enum aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_2H. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment and adjust calculation to ignore qualifier for type 2H. * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
Diffstat (limited to 'include/opcode/aarch64.h')
-rw-r--r--include/opcode/aarch64.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index b8a2c01..80c91d3 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -282,6 +282,7 @@ enum aarch64_opnd_qualifier
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_16B,
+ AARCH64_OPND_QLF_V_2H,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_8H,
AARCH64_OPND_QLF_V_2S,