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authorCary Coutant <ccoutant@gmail.com>2017-09-26 07:33:04 -0700
committerCary Coutant <ccoutant@gmail.com>2017-09-26 07:33:04 -0700
commit00956d3a8ab1b56fcdf63aee4ed5c5a1d46a7a48 (patch)
tree83b6c2e9f6f3fb6269d40275c44a5215e0adf11a /gold
parent33e0a9a056bd23e923b929a4f2ab049ade0b1c32 (diff)
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Fix incorrect register mask.
PR gold/22213 * sparc.cc (Target_sparc): Fix incorrect register mask.
Diffstat (limited to 'gold')
-rw-r--r--gold/ChangeLog5
-rw-r--r--gold/sparc.cc2
2 files changed, 6 insertions, 1 deletions
diff --git a/gold/ChangeLog b/gold/ChangeLog
index 0ac7e9e..697a40a 100644
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,8 @@
+2017-09-26 Cary Coutant <ccoutant@gmail.com>
+
+ PR gold/22213
+ * sparc.cc (Target_sparc): Fix incorrect register mask.
+
2017-09-22 Jim Wilson <jim.wilson@linaro.org>
* aarch64.cc (Target_aarch64::aarch64_info): Set
diff --git a/gold/sparc.cc b/gold/sparc.cc
index 54c7c33..965d993 100644
--- a/gold/sparc.cc
+++ b/gold/sparc.cc
@@ -4164,7 +4164,7 @@ Target_sparc<size, big_endian>::Relocate::relax_call(
if (op3 != 0x3d)
{
// First check RS1
- reg = (delay_insn >> 14) & 0x15;
+ reg = (delay_insn >> 14) & 0x1f;
if (reg == 15)
return;