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authorAlan Modra <amodra@gmail.com>2017-02-22 08:10:58 +1030
committerAlan Modra <amodra@gmail.com>2017-02-22 08:44:41 +1030
commit6528b6eba85f044667876a2ad77d4612a9e5fc65 (patch)
tree2f8b669ea8177a1d29ba53b18b8ed5c62af5dd61 /gold/powerpc.cc
parent1b90b1390679473dd84416e462afa1587769ceec (diff)
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PowerPC ld segfault on script discarding dynamic sections
bfd/ * elf64-ppc.c (ppc64_elf_finish_dynamic_sections): Don't segfault on .got or .plt output section being discarded by script. * elf32-ppc.c (ppc_elf_finish_dynamic_sections): Likewise. Move vxworks splt temp. gold/ * powerpc.cc (Target_powerpc::make_iplt_section): Check that output_section exists before attempting add_output_section_data. (Target_powerpc::make_brlt_section): Likewise.
Diffstat (limited to 'gold/powerpc.cc')
-rw-r--r--gold/powerpc.cc14
1 files changed, 9 insertions, 5 deletions
diff --git a/gold/powerpc.cc b/gold/powerpc.cc
index 4abfcec..1477a10 100644
--- a/gold/powerpc.cc
+++ b/gold/powerpc.cc
@@ -3608,11 +3608,13 @@ Target_powerpc<size, big_endian>::make_iplt_section(Symbol_table* symtab,
this->make_plt_section(symtab, layout);
Reloc_section* iplt_rel = new Reloc_section(false);
- this->rela_dyn_->output_section()->add_output_section_data(iplt_rel);
+ if (this->rela_dyn_->output_section())
+ this->rela_dyn_->output_section()->add_output_section_data(iplt_rel);
this->iplt_
= new Output_data_plt_powerpc<size, big_endian>(this, iplt_rel,
"** IPLT");
- this->plt_->output_section()->add_output_section_data(this->iplt_);
+ if (this->plt_->output_section())
+ this->plt_->output_section()->add_output_section_data(this->iplt_);
}
}
@@ -3708,14 +3710,16 @@ Target_powerpc<size, big_endian>::make_brlt_section(Layout* layout)
{
// When PIC we can't fill in .branch_lt (like .plt it can be
// a bss style section) but must initialise at runtime via
- // dynamic relocats.
+ // dynamic relocations.
this->rela_dyn_section(layout);
brlt_rel = new Reloc_section(false);
- this->rela_dyn_->output_section()->add_output_section_data(brlt_rel);
+ if (this->rela_dyn_->output_section())
+ this->rela_dyn_->output_section()
+ ->add_output_section_data(brlt_rel);
}
this->brlt_section_
= new Output_data_brlt_powerpc<size, big_endian>(this, brlt_rel);
- if (this->plt_ && is_pic)
+ if (this->plt_ && is_pic && this->plt_->output_section())
this->plt_->output_section()
->add_output_section_data(this->brlt_section_);
else