Modify AArch64 Assembly and disassembly functions to be able to fail and report why.

This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.

2 files changed, 11 insertions, 4 deletions

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 8035353..57a4075 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,10 @@
+2018-05-15  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/21446
+	* aarch64-tdep.c (aarch64_analyze_prologue,
+	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
+	Indicate not interested in errors.
+
 2018-05-15  Maciej W. Rozycki  <macro@mips.com>
 
 	* mips-linux-nat.c (mips_linux_nat_target::fetch_registers):
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 3c1f389..c5ed80c 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -244,7 +244,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 
       insn = reader.read (start, 4, byte_order_for_code);
 
-      if (aarch64_decode_insn (insn, &inst, 1) != 0)
+      if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
 	break;
 
       if (inst.opcode->iclass == addsub_imm
@@ -2425,7 +2425,7 @@ aarch64_software_single_step (struct regcache *regcache)
   int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */
   aarch64_inst inst;
 
-  if (aarch64_decode_insn (insn, &inst, 1) != 0)
+  if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
     return {};
 
   /* Look for a Load Exclusive instruction which begins the sequence.  */
@@ -2438,7 +2438,7 @@ aarch64_software_single_step (struct regcache *regcache)
       insn = read_memory_unsigned_integer (loc, insn_size,
 					   byte_order_for_code);
 
-      if (aarch64_decode_insn (insn, &inst, 1) != 0)
+      if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
 	return {};
       /* Check if the instruction is a conditional branch.  */
       if (inst.opcode->iclass == condbranch)
@@ -2731,7 +2731,7 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
   struct aarch64_displaced_step_data dsd;
   aarch64_inst inst;
 
-  if (aarch64_decode_insn (insn, &inst, 1) != 0)
+  if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
     return NULL;
 
   /* Look for a Load Exclusive instruction which begins the sequence.  */