Run clang-format.shusers/simark/clang-format

Change-Id: Ia948cc26d534b0dd02702244d52434b1a2093968

1 files changed, 786 insertions, 448 deletions

diff --git a/gdb/v850-tdep.c b/gdb/v850-tdep.c
index cc7da90..104b601 100644
--- a/gdb/v850-tdep.c
+++ b/gdb/v850-tdep.c
@@ -35,203 +35,220 @@
 #include "gdbarch.h"
 
 enum
-  {
-    /* General purpose registers.  */
-    E_R0_REGNUM,
-    E_R1_REGNUM,
-    E_R2_REGNUM,
-    E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
-    E_R4_REGNUM,
-    E_R5_REGNUM,
-    E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
-    E_R7_REGNUM,
-    E_R8_REGNUM,
-    E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
-    E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
-    E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
-    E_R12_REGNUM,
-    E_R13_REGNUM,
-    E_R14_REGNUM,
-    E_R15_REGNUM,
-    E_R16_REGNUM,
-    E_R17_REGNUM,
-    E_R18_REGNUM,
-    E_R19_REGNUM,
-    E_R20_REGNUM,
-    E_R21_REGNUM,
-    E_R22_REGNUM,
-    E_R23_REGNUM,
-    E_R24_REGNUM,
-    E_R25_REGNUM,
-    E_R26_REGNUM,
-    E_R27_REGNUM,
-    E_R28_REGNUM,
-    E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
-    E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
-    E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
-
-    /* System registers - main banks.  */
-    E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
-    E_R33_REGNUM,
-    E_R34_REGNUM,
-    E_R35_REGNUM,
-    E_R36_REGNUM,
-    E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
-    E_R38_REGNUM,
-    E_R39_REGNUM,
-    E_R40_REGNUM,
-    E_R41_REGNUM,
-    E_R42_REGNUM,
-    E_R43_REGNUM,
-    E_R44_REGNUM,
-    E_R45_REGNUM,
-    E_R46_REGNUM,
-    E_R47_REGNUM,
-    E_R48_REGNUM,
-    E_R49_REGNUM,
-    E_R50_REGNUM,
-    E_R51_REGNUM,
-    E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
-    E_R53_REGNUM,
-    E_R54_REGNUM,
-    E_R55_REGNUM,
-    E_R56_REGNUM,
-    E_R57_REGNUM,
-    E_R58_REGNUM,
-    E_R59_REGNUM,
-    E_R60_REGNUM,
-    E_R61_REGNUM,
-    E_R62_REGNUM,
-    E_R63_REGNUM,
-
-    /* PC.  */
-    E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
-    E_R65_REGNUM,
-    E_NUM_OF_V850_REGS,
-    E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
-
-    /* System registers - MPV (PROT00) bank.  */
-    E_R66_REGNUM = E_NUM_OF_V850_REGS,
-    E_R67_REGNUM,
-    E_R68_REGNUM,
-    E_R69_REGNUM,
-    E_R70_REGNUM,
-    E_R71_REGNUM,
-    E_R72_REGNUM,
-    E_R73_REGNUM,
-    E_R74_REGNUM,
-    E_R75_REGNUM,
-    E_R76_REGNUM,
-    E_R77_REGNUM,
-    E_R78_REGNUM,
-    E_R79_REGNUM,
-    E_R80_REGNUM,
-    E_R81_REGNUM,
-    E_R82_REGNUM,
-    E_R83_REGNUM,
-    E_R84_REGNUM,
-    E_R85_REGNUM,
-    E_R86_REGNUM,
-    E_R87_REGNUM,
-    E_R88_REGNUM,
-    E_R89_REGNUM,
-    E_R90_REGNUM,
-    E_R91_REGNUM,
-    E_R92_REGNUM,
-    E_R93_REGNUM,
-
-    /* System registers - MPU (PROT01) bank.  */
-    E_R94_REGNUM,
-    E_R95_REGNUM,
-    E_R96_REGNUM,
-    E_R97_REGNUM,
-    E_R98_REGNUM,
-    E_R99_REGNUM,
-    E_R100_REGNUM,
-    E_R101_REGNUM,
-    E_R102_REGNUM,
-    E_R103_REGNUM,
-    E_R104_REGNUM,
-    E_R105_REGNUM,
-    E_R106_REGNUM,
-    E_R107_REGNUM,
-    E_R108_REGNUM,
-    E_R109_REGNUM,
-    E_R110_REGNUM,
-    E_R111_REGNUM,
-    E_R112_REGNUM,
-    E_R113_REGNUM,
-    E_R114_REGNUM,
-    E_R115_REGNUM,
-    E_R116_REGNUM,
-    E_R117_REGNUM,
-    E_R118_REGNUM,
-    E_R119_REGNUM,
-    E_R120_REGNUM,
-    E_R121_REGNUM,
-
-    /* FPU system registers.  */
-    E_R122_REGNUM,
-    E_R123_REGNUM,
-    E_R124_REGNUM,
-    E_R125_REGNUM,
-    E_R126_REGNUM,
-    E_R127_REGNUM,
-    E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
-    E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
-    E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
-    E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
-    E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
-    E_R133_REGNUM,
-    E_R134_REGNUM,
-    E_R135_REGNUM,
-    E_R136_REGNUM,
-    E_R137_REGNUM,
-    E_R138_REGNUM,
-    E_R139_REGNUM,
-    E_R140_REGNUM,
-    E_R141_REGNUM,
-    E_R142_REGNUM,
-    E_R143_REGNUM,
-    E_R144_REGNUM,
-    E_R145_REGNUM,
-    E_R146_REGNUM,
-    E_R147_REGNUM,
-    E_R148_REGNUM,
-    E_R149_REGNUM,
-    E_NUM_OF_V850E2_REGS,
-
-    /* v850e3v5 system registers, selID 1 thru 7.  */
-    E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
-    E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
-
-    E_SELID_2_R0_REGNUM,
-    E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
-
-    E_SELID_3_R0_REGNUM,
-    E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
-
-    E_SELID_4_R0_REGNUM,
-    E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
-
-    E_SELID_5_R0_REGNUM,
-    E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
-
-    E_SELID_6_R0_REGNUM,
-    E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
-
-    E_SELID_7_R0_REGNUM,
-    E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
-
-    /* v850e3v5 vector registers.  */
-    E_VR0_REGNUM,
-    E_VR31_REGNUM = E_VR0_REGNUM + 31,
-
-    E_NUM_OF_V850E3V5_REGS,
-
-    /* Total number of possible registers.  */
-    E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
-  };
+{
+  /* General purpose registers.  */
+  E_R0_REGNUM,
+  E_R1_REGNUM,
+  E_R2_REGNUM,
+  E_R3_REGNUM,
+  E_SP_REGNUM = E_R3_REGNUM,
+  E_R4_REGNUM,
+  E_R5_REGNUM,
+  E_R6_REGNUM,
+  E_ARG0_REGNUM = E_R6_REGNUM,
+  E_R7_REGNUM,
+  E_R8_REGNUM,
+  E_R9_REGNUM,
+  E_ARGLAST_REGNUM = E_R9_REGNUM,
+  E_R10_REGNUM,
+  E_V0_REGNUM = E_R10_REGNUM,
+  E_R11_REGNUM,
+  E_V1_REGNUM = E_R11_REGNUM,
+  E_R12_REGNUM,
+  E_R13_REGNUM,
+  E_R14_REGNUM,
+  E_R15_REGNUM,
+  E_R16_REGNUM,
+  E_R17_REGNUM,
+  E_R18_REGNUM,
+  E_R19_REGNUM,
+  E_R20_REGNUM,
+  E_R21_REGNUM,
+  E_R22_REGNUM,
+  E_R23_REGNUM,
+  E_R24_REGNUM,
+  E_R25_REGNUM,
+  E_R26_REGNUM,
+  E_R27_REGNUM,
+  E_R28_REGNUM,
+  E_R29_REGNUM,
+  E_FP_REGNUM = E_R29_REGNUM,
+  E_R30_REGNUM,
+  E_EP_REGNUM = E_R30_REGNUM,
+  E_R31_REGNUM,
+  E_LP_REGNUM = E_R31_REGNUM,
+
+  /* System registers - main banks.  */
+  E_R32_REGNUM,
+  E_SR0_REGNUM = E_R32_REGNUM,
+  E_R33_REGNUM,
+  E_R34_REGNUM,
+  E_R35_REGNUM,
+  E_R36_REGNUM,
+  E_R37_REGNUM,
+  E_PS_REGNUM = E_R37_REGNUM,
+  E_R38_REGNUM,
+  E_R39_REGNUM,
+  E_R40_REGNUM,
+  E_R41_REGNUM,
+  E_R42_REGNUM,
+  E_R43_REGNUM,
+  E_R44_REGNUM,
+  E_R45_REGNUM,
+  E_R46_REGNUM,
+  E_R47_REGNUM,
+  E_R48_REGNUM,
+  E_R49_REGNUM,
+  E_R50_REGNUM,
+  E_R51_REGNUM,
+  E_R52_REGNUM,
+  E_CTBP_REGNUM = E_R52_REGNUM,
+  E_R53_REGNUM,
+  E_R54_REGNUM,
+  E_R55_REGNUM,
+  E_R56_REGNUM,
+  E_R57_REGNUM,
+  E_R58_REGNUM,
+  E_R59_REGNUM,
+  E_R60_REGNUM,
+  E_R61_REGNUM,
+  E_R62_REGNUM,
+  E_R63_REGNUM,
+
+  /* PC.  */
+  E_R64_REGNUM,
+  E_PC_REGNUM = E_R64_REGNUM,
+  E_R65_REGNUM,
+  E_NUM_OF_V850_REGS,
+  E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
+
+  /* System registers - MPV (PROT00) bank.  */
+  E_R66_REGNUM = E_NUM_OF_V850_REGS,
+  E_R67_REGNUM,
+  E_R68_REGNUM,
+  E_R69_REGNUM,
+  E_R70_REGNUM,
+  E_R71_REGNUM,
+  E_R72_REGNUM,
+  E_R73_REGNUM,
+  E_R74_REGNUM,
+  E_R75_REGNUM,
+  E_R76_REGNUM,
+  E_R77_REGNUM,
+  E_R78_REGNUM,
+  E_R79_REGNUM,
+  E_R80_REGNUM,
+  E_R81_REGNUM,
+  E_R82_REGNUM,
+  E_R83_REGNUM,
+  E_R84_REGNUM,
+  E_R85_REGNUM,
+  E_R86_REGNUM,
+  E_R87_REGNUM,
+  E_R88_REGNUM,
+  E_R89_REGNUM,
+  E_R90_REGNUM,
+  E_R91_REGNUM,
+  E_R92_REGNUM,
+  E_R93_REGNUM,
+
+  /* System registers - MPU (PROT01) bank.  */
+  E_R94_REGNUM,
+  E_R95_REGNUM,
+  E_R96_REGNUM,
+  E_R97_REGNUM,
+  E_R98_REGNUM,
+  E_R99_REGNUM,
+  E_R100_REGNUM,
+  E_R101_REGNUM,
+  E_R102_REGNUM,
+  E_R103_REGNUM,
+  E_R104_REGNUM,
+  E_R105_REGNUM,
+  E_R106_REGNUM,
+  E_R107_REGNUM,
+  E_R108_REGNUM,
+  E_R109_REGNUM,
+  E_R110_REGNUM,
+  E_R111_REGNUM,
+  E_R112_REGNUM,
+  E_R113_REGNUM,
+  E_R114_REGNUM,
+  E_R115_REGNUM,
+  E_R116_REGNUM,
+  E_R117_REGNUM,
+  E_R118_REGNUM,
+  E_R119_REGNUM,
+  E_R120_REGNUM,
+  E_R121_REGNUM,
+
+  /* FPU system registers.  */
+  E_R122_REGNUM,
+  E_R123_REGNUM,
+  E_R124_REGNUM,
+  E_R125_REGNUM,
+  E_R126_REGNUM,
+  E_R127_REGNUM,
+  E_R128_REGNUM,
+  E_FPSR_REGNUM = E_R128_REGNUM,
+  E_R129_REGNUM,
+  E_FPEPC_REGNUM = E_R129_REGNUM,
+  E_R130_REGNUM,
+  E_FPST_REGNUM = E_R130_REGNUM,
+  E_R131_REGNUM,
+  E_FPCC_REGNUM = E_R131_REGNUM,
+  E_R132_REGNUM,
+  E_FPCFG_REGNUM = E_R132_REGNUM,
+  E_R133_REGNUM,
+  E_R134_REGNUM,
+  E_R135_REGNUM,
+  E_R136_REGNUM,
+  E_R137_REGNUM,
+  E_R138_REGNUM,
+  E_R139_REGNUM,
+  E_R140_REGNUM,
+  E_R141_REGNUM,
+  E_R142_REGNUM,
+  E_R143_REGNUM,
+  E_R144_REGNUM,
+  E_R145_REGNUM,
+  E_R146_REGNUM,
+  E_R147_REGNUM,
+  E_R148_REGNUM,
+  E_R149_REGNUM,
+  E_NUM_OF_V850E2_REGS,
+
+  /* v850e3v5 system registers, selID 1 thru 7.  */
+  E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
+  E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
+
+  E_SELID_2_R0_REGNUM,
+  E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
+
+  E_SELID_3_R0_REGNUM,
+  E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
+
+  E_SELID_4_R0_REGNUM,
+  E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
+
+  E_SELID_5_R0_REGNUM,
+  E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
+
+  E_SELID_6_R0_REGNUM,
+  E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
+
+  E_SELID_7_R0_REGNUM,
+  E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
+
+  /* v850e3v5 vector registers.  */
+  E_VR0_REGNUM,
+  E_VR31_REGNUM = E_VR0_REGNUM + 31,
+
+  E_NUM_OF_V850E3V5_REGS,
+
+  /* Total number of possible registers.  */
+  E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
+};
 
 enum
 {
@@ -272,46 +289,48 @@ struct v850_gdbarch_tdep : gdbarch_tdep_base
   int e_machine = 0;
 
   /* Which ABI are we using?  */
-  enum v850_abi abi {};
+  enum v850_abi abi
+  {
+  };
+
   int eight_byte_align = 0;
 };
 
 struct v850_frame_cache
-{ 
+{
   /* Base address.  */
   CORE_ADDR base;
   LONGEST sp_offset;
   CORE_ADDR pc;
-  
+
   /* Flag showing that a frame has been created in the prologue code.  */
   int uses_fp;
-  
+
   /* Saved registers.  */
   trad_frame_saved_reg *saved_regs;
 };
 
 /* Info gleaned from scanning a function's prologue.  */
-struct pifsr		/* Info about one saved register.  */
+struct pifsr /* Info about one saved register.  */
 {
-  int offset;		/* Offset from sp or fp.  */
-  int cur_frameoffset;	/* Current frameoffset.  */
-  int reg;		/* Saved register number.  */
+  int offset;	       /* Offset from sp or fp.  */
+  int cur_frameoffset; /* Current frameoffset.  */
+  int reg;	       /* Saved register number.  */
 };
 
 static const char *
 v850_register_name (struct gdbarch *gdbarch, int regnum)
 {
-  static const char *v850_reg_names[] =
-  { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 
-    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
-    "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
-    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
-    "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
-    "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
-    "pc", "fp"
-  };
+  static const char *v850_reg_names[]
+    = { "r0",	"r1",	 "r2",	 "r3",	  "r4",	  "r5",	  "r6",	  "r7",
+	"r8",	"r9",	 "r10",	 "r11",	  "r12",  "r13",  "r14",  "r15",
+	"r16",	"r17",	 "r18",	 "r19",	  "r20",  "r21",  "r22",  "r23",
+	"r24",	"r25",	 "r26",	 "r27",	  "r28",  "r29",  "r30",  "r31",
+	"eipc", "eipsw", "fepc", "fepsw", "ecr",  "psw",  "sr6",  "sr7",
+	"sr8",	"sr9",	 "sr10", "sr11",  "sr12", "sr13", "sr14", "sr15",
+	"sr16", "sr17",	 "sr18", "sr19",  "sr20", "sr21", "sr22", "sr23",
+	"sr24", "sr25",	 "sr26", "sr27",  "sr28", "sr29", "sr30", "sr31",
+	"pc",	"fp" };
   gdb_static_assert (E_NUM_OF_V850_REGS == ARRAY_SIZE (v850_reg_names));
   return v850_reg_names[regnum];
 }
@@ -319,18 +338,16 @@ v850_register_name (struct gdbarch *gdbarch, int regnum)
 static const char *
 v850e_register_name (struct gdbarch *gdbarch, int regnum)
 {
-  static const char *v850e_reg_names[] =
-  {
-    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
-    "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
-    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
-    "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
-    "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
-    "pc", "fp"
-  };
+  static const char *v850e_reg_names[]
+    = { "r0",	"r1",	 "r2",	 "r3",	  "r4",	  "r5",	  "r6",	  "r7",
+	"r8",	"r9",	 "r10",	 "r11",	  "r12",  "r13",  "r14",  "r15",
+	"r16",	"r17",	 "r18",	 "r19",	  "r20",  "r21",  "r22",  "r23",
+	"r24",	"r25",	 "r26",	 "r27",	  "r28",  "r29",  "r30",  "r31",
+	"eipc", "eipsw", "fepc", "fepsw", "ecr",  "psw",  "sr6",  "sr7",
+	"sr8",	"sr9",	 "sr10", "sr11",  "sr12", "sr13", "sr14", "sr15",
+	"ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
+	"sr24", "sr25",	 "sr26", "sr27",  "sr28", "sr29", "sr30", "sr31",
+	"pc",	"fp" };
   gdb_static_assert (E_NUM_OF_V850E_REGS == ARRAY_SIZE (v850e_reg_names));
   return v850e_reg_names[regnum];
 }
@@ -338,41 +355,34 @@ v850e_register_name (struct gdbarch *gdbarch, int regnum)
 static const char *
 v850e2_register_name (struct gdbarch *gdbarch, int regnum)
 {
-  static const char *v850e2_reg_names[] =
-  {
+  static const char *v850e2_reg_names[] = {
     /* General purpose registers.  */
-    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
+    "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
+    "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 
     /* System registers - main banks.  */
-    "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
-    "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
-    "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
-    "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
-
+    "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg", "", "", "",
+    "sccfg", "scbp", "eiic", "feic", "dbic", "ctpc", "ctpsw", "dbpc", "dbpsw",
+    "ctbp", "dir", "", "", "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
 
     /* PC.  */
     "pc", "",
 
     /* System registers - MPV (PROT00) bank.  */
-    "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
-    "vpecr", "vptid", "vpadr", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
+    "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "", "vpecr",
+    "vptid", "vpadr", "", "", "", "", "", "", "", "", "", "", "", "", "",
     "mca", "mcs", "mcc", "mcr",
 
     /* System registers - MPU (PROT01) bank.  */
-    "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
-    "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
-    "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
-    "dpa4l", "dpa4u", "dpa5l", "dpa5u",
+    "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u", "ipa1l", "ipa1u",
+    "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u", "dpa0l", "dpa0u",
+    "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u", "dpa4l", "dpa4u",
+    "dpa5l", "dpa5u",
 
     /* FPU system registers.  */
-    "", "", "", "", "", "", "fpsr", "fpepc",
-    "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "fpspc"
+    "", "", "", "", "", "", "fpsr", "fpepc", "fpst", "fpcc", "fpcfg", "fpec",
+    "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "fpspc"
   };
   if (regnum >= E_NUM_OF_V850E2_REGS)
     return "";
@@ -384,97 +394,444 @@ v850e2_register_name (struct gdbarch *gdbarch, int regnum)
 static const char *
 v850e3v5_register_name (struct gdbarch *gdbarch, int regnum)
 {
-  static const char *v850e3v5_reg_names[] =
-  {
+  static const char *v850e3v5_reg_names[] = {
     /* General purpose registers.  */
-    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+    "r0",
+    "r1",
+    "r2",
+    "r3",
+    "r4",
+    "r5",
+    "r6",
+    "r7",
+    "r8",
+    "r9",
+    "r10",
+    "r11",
+    "r12",
+    "r13",
+    "r14",
+    "r15",
+    "r16",
+    "r17",
+    "r18",
+    "r19",
+    "r20",
+    "r21",
+    "r22",
+    "r23",
+    "r24",
+    "r25",
+    "r26",
+    "r27",
+    "r28",
+    "r29",
+    "r30",
+    "r31",
 
     /* selID 0, not including FPU registers.  The FPU registers are
        listed later on.  */
-    "eipc", "eipsw", "fepc", "fepsw",
-    "", "psw", "" /* fpsr */, "" /* fpepc */,
-    "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
-    "sesr", "eiic", "feic", "",
-    "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
-    "", "", "", "", "eiwr", "fewr", "", "bsel",
-
+    "eipc",
+    "eipsw",
+    "fepc",
+    "fepsw",
+    "",
+    "psw",
+    "" /* fpsr */,
+    "" /* fpepc */,
+    "" /* fpst */,
+    "" /* fpcc */,
+    "" /* fpcfg */,
+    "" /* fpec */,
+    "sesr",
+    "eiic",
+    "feic",
+    "",
+    "ctpc",
+    "ctpsw",
+    "",
+    "",
+    "ctbp",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "eiwr",
+    "fewr",
+    "",
+    "bsel",
 
     /* PC.  */
-    "pc", "",
+    "pc",
+    "",
 
     /* v850e2 MPV bank.  */
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
 
     /* Skip v850e2 MPU bank.  It's tempting to reuse these, but we need
        32 entries for this bank.  */
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
 
     /* FPU system registers.  These are actually in selID 0, but
        are placed here to preserve register numbering compatibility
        with previous architectures.  */
-    "", "", "", "", "", "", "fpsr", "fpepc",
-    "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "fpsr",
+    "fpepc",
+    "fpst",
+    "fpcc",
+    "fpcfg",
+    "fpec",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
 
     /* selID 1.  */
-    "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
-    "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
-    "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
-    "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
+    "mcfg0",
+    "mcfg1",
+    "rbase",
+    "ebase",
+    "intbp",
+    "mctl",
+    "pid",
+    "fpipr",
+    "",
+    "",
+    "tcsel",
+    "sccfg",
+    "scbp",
+    "hvccfg",
+    "hvcbp",
+    "vsel",
+    "vmprt0",
+    "vmprt1",
+    "vmprt2",
+    "",
+    "",
+    "",
+    "",
+    "vmscctl",
+    "vmsctbl0",
+    "vmsctbl1",
+    "vmsctbl2",
+    "vmsctbl3",
+    "",
+    "",
+    "",
+    "",
 
     /* selID 2.  */
-    "htcfg0", "", "", "", "", "htctl", "mea", "asid",
-    "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
-    "tlbsch", "", "", "", "", "", "", "htscctl",
-    "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
-    "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
+    "htcfg0",
+    "",
+    "",
+    "",
+    "",
+    "htctl",
+    "mea",
+    "asid",
+    "mei",
+    "ispr",
+    "pmr",
+    "icsr",
+    "intcfg",
+    "",
+    "",
+    "",
+    "tlbsch",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "htscctl",
+    "htsctbl0",
+    "htsctbl1",
+    "htsctbl2",
+    "htsctbl3",
+    "htsctbl4",
+    "htsctbl5",
+    "htsctbl6",
+    "htsctbl7",
 
     /* selID 3.  */
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
-    "", "", "", "", "", "", "", "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
 
     /* selID 4.  */
-    "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
-    "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
-    "ictagl", "ictagh", "icdatl", "icdath",
-    "dctagl", "dctagh", "dcdatl", "dcdath",
-    "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
+    "tlbidx",
+    "",
+    "",
+    "",
+    "telo0",
+    "telo1",
+    "tehi0",
+    "tehi1",
+    "",
+    "",
+    "tlbcfg",
+    "",
+    "bwerrl",
+    "bwerrh",
+    "brerrl",
+    "brerrh",
+    "ictagl",
+    "ictagh",
+    "icdatl",
+    "icdath",
+    "dctagl",
+    "dctagh",
+    "dcdatl",
+    "dcdath",
+    "icctrl",
+    "dcctrl",
+    "iccfg",
+    "dccfg",
+    "icerr",
+    "dcerr",
+    "",
+    "",
 
     /* selID 5.  */
-    "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
-    "mca", "mcs", "mcc", "mcr", "", "", "", "",
-    "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
-    "", "", "", "", "", "", "", "",
+    "mpm",
+    "mprc",
+    "",
+    "",
+    "mpbrgn",
+    "mptrgn",
+    "",
+    "",
+    "mca",
+    "mcs",
+    "mcc",
+    "mcr",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "mpprt0",
+    "mpprt1",
+    "mpprt2",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
+    "",
 
     /* selID 6.  */
-    "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
-    "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
-    "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
-    "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
+    "mpla0",
+    "mpua0",
+    "mpat0",
+    "",
+    "mpla1",
+    "mpua1",
+    "mpat1",
+    "",
+    "mpla2",
+    "mpua2",
+    "mpat2",
+    "",
+    "mpla3",
+    "mpua3",
+    "mpat3",
+    "",
+    "mpla4",
+    "mpua4",
+    "mpat4",
+    "",
+    "mpla5",
+    "mpua5",
+    "mpat5",
+    "",
+    "mpla6",
+    "mpua6",
+    "mpat6",
+    "",
+    "mpla7",
+    "mpua7",
+    "mpat7",
+    "",
 
     /* selID 7.  */
-    "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
-    "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
-    "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
-    "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
+    "mpla8",
+    "mpua8",
+    "mpat8",
+    "",
+    "mpla9",
+    "mpua9",
+    "mpat9",
+    "",
+    "mpla10",
+    "mpua10",
+    "mpat10",
+    "",
+    "mpla11",
+    "mpua11",
+    "mpat11",
+    "",
+    "mpla12",
+    "mpua12",
+    "mpat12",
+    "",
+    "mpla13",
+    "mpua13",
+    "mpat13",
+    "",
+    "mpla14",
+    "mpua14",
+    "mpat14",
+    "",
+    "mpla15",
+    "mpua15",
+    "mpat15",
+    "",
 
     /* Vector Registers */
-    "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
-    "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
-    "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
-    "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
+    "vr0",
+    "vr1",
+    "vr2",
+    "vr3",
+    "vr4",
+    "vr5",
+    "vr6",
+    "vr7",
+    "vr8",
+    "vr9",
+    "vr10",
+    "vr11",
+    "vr12",
+    "vr13",
+    "vr14",
+    "vr15",
+    "vr16",
+    "vr17",
+    "vr18",
+    "vr19",
+    "vr20",
+    "vr21",
+    "vr22",
+    "vr23",
+    "vr24",
+    "vr25",
+    "vr26",
+    "vr27",
+    "vr28",
+    "vr29",
+    "vr30",
+    "vr31",
   };
 
   gdb_static_assert (E_NUM_OF_V850E3V5_REGS
@@ -497,8 +854,7 @@ v850_register_type (struct gdbarch *gdbarch, int regnum)
 static int
 v850_type_is_scalar (struct type *t)
 {
-  return (t->code () != TYPE_CODE_STRUCT
-	  && t->code () != TYPE_CODE_UNION
+  return (t->code () != TYPE_CODE_STRUCT && t->code () != TYPE_CODE_UNION
 	  && t->code () != TYPE_CODE_ARRAY);
 }
 
@@ -530,9 +886,8 @@ v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
   /* The value is a structure or union with a single element and that
      element is either a single basic type or an array of a single basic
      type whose size is greater than or equal to 4 -> returned in register.  */
-  if ((type->code () == TYPE_CODE_STRUCT
-       || type->code () == TYPE_CODE_UNION)
-       && type->num_fields () == 1)
+  if ((type->code () == TYPE_CODE_STRUCT || type->code () == TYPE_CODE_UNION)
+      && type->num_fields () == 1)
     {
       fld_type = type->field (0).type ();
       if (v850_type_is_scalar (fld_type) && fld_type->length () >= 4)
@@ -566,7 +921,7 @@ v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
 	}
       return 0;
     }
-    
+
   /* The value is a union which contains at least one field which
      would be returned in registers according to these rules ->
      returned in register.  */
@@ -594,7 +949,7 @@ struct reg_list
 /* Helper function for v850_scan_prologue to handle prepare instruction.  */
 
 static void
-v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
+v850_handle_prepare (int insn, int insn2, CORE_ADDR *current_pc_ptr,
 		     struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
 {
   CORE_ADDR current_pc = *current_pc_ptr;
@@ -602,29 +957,28 @@ v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
   long next = insn2 & 0xffff;
   long list12 = ((insn & 1) << 16) + (next & 0xffe0);
   long offset = (insn & 0x3e) << 1;
-  static struct reg_list reg_table[] =
-  {
-    {0x00800, 20},		/* r20 */
-    {0x00400, 21},		/* r21 */
-    {0x00200, 22},		/* r22 */
-    {0x00100, 23},		/* r23 */
-    {0x08000, 24},		/* r24 */
-    {0x04000, 25},		/* r25 */
-    {0x02000, 26},		/* r26 */
-    {0x01000, 27},		/* r27 */
-    {0x00080, 28},		/* r28 */
-    {0x00040, 29},		/* r29 */
-    {0x10000, 30},		/* ep */
-    {0x00020, 31},		/* lp */
-    {0, 0}			/* end of table */
+  static struct reg_list reg_table[] = {
+    { 0x00800, 20 }, /* r20 */
+    { 0x00400, 21 }, /* r21 */
+    { 0x00200, 22 }, /* r22 */
+    { 0x00100, 23 }, /* r23 */
+    { 0x08000, 24 }, /* r24 */
+    { 0x04000, 25 }, /* r25 */
+    { 0x02000, 26 }, /* r26 */
+    { 0x01000, 27 }, /* r27 */
+    { 0x00080, 28 }, /* r28 */
+    { 0x00040, 29 }, /* r29 */
+    { 0x10000, 30 }, /* ep */
+    { 0x00020, 31 }, /* lp */
+    { 0, 0 }	     /* end of table */
   };
   int i;
 
-  if ((next & 0x1f) == 0x0b)		/* skip imm16 argument */
+  if ((next & 0x1f) == 0x0b) /* skip imm16 argument */
     current_pc += 2;
-  else if ((next & 0x1f) == 0x13)	/* skip imm16 argument */
+  else if ((next & 0x1f) == 0x13) /* skip imm16 argument */
     current_pc += 2;
-  else if ((next & 0x1f) == 0x1b)	/* skip imm32 argument */
+  else if ((next & 0x1f) == 0x1b) /* skip imm32 argument */
     current_pc += 4;
 
   /* Calculate the total size of the saved registers, and add it to the
@@ -658,7 +1012,6 @@ v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
   *pifsr_ptr = pifsr;
 }
 
-
 /* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
    The SR bit of the register list is not supported.  gcc does not generate
    this bit.  */
@@ -670,45 +1023,43 @@ v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
   struct pifsr *pifsr = *pifsr_ptr;
   long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
   long offset = 0;
-  static struct reg_list pushml_reg_table[] =
-  {
-    {0x80000, E_PS_REGNUM},	/* PSW */
-    {0x40000, 1},		/* r1 */
-    {0x20000, 2},		/* r2 */
-    {0x10000, 3},		/* r3 */
-    {0x00800, 4},		/* r4 */
-    {0x00400, 5},		/* r5 */
-    {0x00200, 6},		/* r6 */
-    {0x00100, 7},		/* r7 */
-    {0x08000, 8},		/* r8 */
-    {0x04000, 9},		/* r9 */
-    {0x02000, 10},		/* r10 */
-    {0x01000, 11},		/* r11 */
-    {0x00080, 12},		/* r12 */
-    {0x00040, 13},		/* r13 */
-    {0x00020, 14},		/* r14 */
-    {0x00010, 15},		/* r15 */
-    {0, 0}			/* end of table */
+  static struct reg_list pushml_reg_table[] = {
+    { 0x80000, E_PS_REGNUM }, /* PSW */
+    { 0x40000, 1 },	      /* r1 */
+    { 0x20000, 2 },	      /* r2 */
+    { 0x10000, 3 },	      /* r3 */
+    { 0x00800, 4 },	      /* r4 */
+    { 0x00400, 5 },	      /* r5 */
+    { 0x00200, 6 },	      /* r6 */
+    { 0x00100, 7 },	      /* r7 */
+    { 0x08000, 8 },	      /* r8 */
+    { 0x04000, 9 },	      /* r9 */
+    { 0x02000, 10 },	      /* r10 */
+    { 0x01000, 11 },	      /* r11 */
+    { 0x00080, 12 },	      /* r12 */
+    { 0x00040, 13 },	      /* r13 */
+    { 0x00020, 14 },	      /* r14 */
+    { 0x00010, 15 },	      /* r15 */
+    { 0, 0 }		      /* end of table */
   };
-  static struct reg_list pushmh_reg_table[] =
-  {
-    {0x80000, 16},		/* r16 */
-    {0x40000, 17},		/* r17 */
-    {0x20000, 18},		/* r18 */
-    {0x10000, 19},		/* r19 */
-    {0x00800, 20},		/* r20 */
-    {0x00400, 21},		/* r21 */
-    {0x00200, 22},		/* r22 */
-    {0x00100, 23},		/* r23 */
-    {0x08000, 24},		/* r24 */
-    {0x04000, 25},		/* r25 */
-    {0x02000, 26},		/* r26 */
-    {0x01000, 27},		/* r27 */
-    {0x00080, 28},		/* r28 */
-    {0x00040, 29},		/* r29 */
-    {0x00010, 30},		/* r30 */
-    {0x00020, 31},		/* r31 */
-    {0, 0}			/* end of table */
+  static struct reg_list pushmh_reg_table[] = {
+    { 0x80000, 16 }, /* r16 */
+    { 0x40000, 17 }, /* r17 */
+    { 0x20000, 18 }, /* r18 */
+    { 0x10000, 19 }, /* r19 */
+    { 0x00800, 20 }, /* r20 */
+    { 0x00400, 21 }, /* r21 */
+    { 0x00200, 22 }, /* r22 */
+    { 0x00100, 23 }, /* r23 */
+    { 0x08000, 24 }, /* r24 */
+    { 0x04000, 25 }, /* r25 */
+    { 0x02000, 26 }, /* r26 */
+    { 0x01000, 27 }, /* r27 */
+    { 0x00080, 28 }, /* r28 */
+    { 0x00040, 29 }, /* r29 */
+    { 0x00010, 30 }, /* r30 */
+    { 0x00020, 31 }, /* r31 */
+    { 0, 0 }	     /* end of table */
   };
   struct reg_list *reg_table;
   int i;
@@ -755,12 +1106,11 @@ v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
 static int
 v850_is_save_register (int reg)
 {
- /* The caller-save registers are R2, R20 - R29 and R31.  All other
+  /* The caller-save registers are R2, R20 - R29 and R31.  All other
     registers are either special purpose (PC, SP), argument registers,
     or just considered free for use in the caller.  */
- return reg == E_R2_REGNUM
-	|| (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
-	|| reg == E_R31_REGNUM;
+  return reg == E_R2_REGNUM || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
+	 || reg == E_R31_REGNUM;
 }
 
 /* Scan the prologue of the function that contains PC, and record what
@@ -772,9 +1122,9 @@ v850_is_save_register (int reg)
    prologue.  */
 
 static CORE_ADDR
-v850_analyze_prologue (struct gdbarch *gdbarch,
-		       CORE_ADDR func_addr, CORE_ADDR pc,
-		       struct v850_frame_cache *pi, ULONGEST ctbp)
+v850_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR func_addr,
+		       CORE_ADDR pc, struct v850_frame_cache *pi,
+		       ULONGEST ctbp)
 {
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   CORE_ADDR prologue_end, current_pc;
@@ -810,73 +1160,73 @@ v850_analyze_prologue (struct gdbarch *gdbarch,
 
       insn = read_memory_integer (current_pc, 2, byte_order);
       current_pc += 2;
-      if ((insn & 0x0780) >= 0x0600)	/* Four byte instruction?  */
+      if ((insn & 0x0780) >= 0x0600) /* Four byte instruction?  */
 	{
 	  insn2 = read_memory_integer (current_pc, 2, byte_order);
 	  current_pc += 2;
 	}
 
       if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
-	{			/* jarl <func>,10 */
+	{ /* jarl <func>,10 */
 	  long low_disp = insn2 & ~(long) 1;
-	  long disp = (((((insn & 0x3f) << 16) + low_disp)
-			& ~(long) 1) ^ 0x00200000) - 0x00200000;
+	  long disp
+	    = (((((insn & 0x3f) << 16) + low_disp) & ~(long) 1) ^ 0x00200000)
+	      - 0x00200000;
 
 	  save_pc = current_pc;
 	  save_end = prologue_end;
 	  regsave_func_p = 1;
 	  current_pc += disp - 4;
-	  prologue_end = (current_pc
-			  + (2 * 3)	/* moves to/from ep */
-			  + 4		/* addi <const>,sp,sp */
-			  + 2		/* jmp [r10] */
-			  + (2 * 12)	/* sst.w to save r2, r20-r29, r31 */
-			  + 20);	/* slop area */
+	  prologue_end = (current_pc + (2 * 3) /* moves to/from ep */
+			  + 4		       /* addi <const>,sp,sp */
+			  + 2		       /* jmp [r10] */
+			  + (2 * 12) /* sst.w to save r2, r20-r29, r31 */
+			  + 20);     /* slop area */
 	}
       else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
-	{			/* callt <imm6> */
+	{ /* callt <imm6> */
 	  long adr = ctbp + ((insn & 0x3f) << 1);
 
 	  save_pc = current_pc;
 	  save_end = prologue_end;
 	  regsave_func_p = 1;
-	  current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
-			       & 0xffff);
-	  prologue_end = (current_pc
-			  + (2 * 3)	/* prepare list2,imm5,sp/imm */
-			  + 4		/* ctret */
-			  + 20);	/* slop area */
+	  current_pc
+	    = ctbp
+	      + (read_memory_unsigned_integer (adr, 2, byte_order) & 0xffff);
+	  prologue_end = (current_pc + (2 * 3) /* prepare list2,imm5,sp/imm */
+			  + 4		       /* ctret */
+			  + 20);	       /* slop area */
 	  continue;
 	}
-      else if ((insn & 0xffc0) == 0x0780)	/* prepare list2,imm5 */
+      else if ((insn & 0xffc0) == 0x0780) /* prepare list2,imm5 */
 	{
 	  v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
 	  continue;
 	}
       else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
-	{			/* ctret after processing register save.  */
+	{ /* ctret after processing register save.  */
 	  current_pc = save_pc;
 	  prologue_end = save_end;
 	  regsave_func_p = 0;
 	  continue;
 	}
       else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
-	{			/* pushml, pushmh */
+	{ /* pushml, pushmh */
 	  v850_handle_pushm (insn, insn2, pi, &pifsr);
 	  continue;
 	}
       else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
-	{			/* jmp after processing register save.  */
+	{ /* jmp after processing register save.  */
 	  current_pc = save_pc;
 	  prologue_end = save_end;
 	  regsave_func_p = 0;
 	  continue;
 	}
-      else if ((insn & 0x07c0) == 0x0780	/* jarl or jr */
-	       || (insn & 0xffe0) == 0x0060	/* jmp */
-	       || (insn & 0x0780) == 0x0580)	/* branch */
+      else if ((insn & 0x07c0) == 0x0780     /* jarl or jr */
+	       || (insn & 0xffe0) == 0x0060  /* jmp */
+	       || (insn & 0x0780) == 0x0580) /* branch */
 	{
-	  break;		/* Ran into end of prologue.  */
+	  break; /* Ran into end of prologue.  */
 	}
 
       else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
@@ -894,7 +1244,8 @@ v850_analyze_prologue (struct gdbarch *gdbarch,
       else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
 	/* movea lo(const),r12,r12 */
 	r12_tmp += insn2;
-      else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
+      else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM)
+	       && r12_tmp)
 	/* add r12,sp */
 	pi->sp_offset += r12_tmp;
       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
@@ -903,11 +1254,9 @@ v850_analyze_prologue (struct gdbarch *gdbarch,
       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
 	/* mov r1,ep */
 	ep_used = 0;
-      else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)	
-		|| (pi->uses_fp
-		    && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
-	       && pifsr
-	       && v850_is_save_register (reg = (insn >> 11) & 0x1f))
+      else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
+		|| (pi->uses_fp && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
+	       && pifsr && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 	{
 	  /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
 	  pifsr->reg = reg;
@@ -915,9 +1264,7 @@ v850_analyze_prologue (struct gdbarch *gdbarch,
 	  pifsr->cur_frameoffset = pi->sp_offset;
 	  pifsr++;
 	}
-      else if (ep_used
-	       && ((insn & 0x0781) == 0x0501)
-	       && pifsr
+      else if (ep_used && ((insn & 0x0781) == 0x0501) && pifsr
 	       && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 	{
 	  /* sst.w <reg>,<offset>[ep] */
@@ -1006,13 +1353,9 @@ v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
    Stack space for the args has NOT been allocated: that job is up to us.  */
 
 static CORE_ADDR
-v850_push_dummy_call (struct gdbarch *gdbarch,
-		      struct value *function,
-		      struct regcache *regcache,
-		      CORE_ADDR bp_addr,
-		      int nargs,
-		      struct value **args,
-		      CORE_ADDR sp,
+v850_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+		      struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
+		      struct value **args, CORE_ADDR sp,
 		      function_call_return_method return_method,
 		      CORE_ADDR struct_addr)
 {
@@ -1146,9 +1489,9 @@ v850_store_return_value (struct type *type, struct regcache *regcache,
   int len = type->length ();
 
   if (len <= v850_reg_size)
-      regcache_cooked_write_unsigned
-	(regcache, E_V0_REGNUM,
-	 extract_unsigned_integer (valbuf, len, byte_order));
+    regcache_cooked_write_unsigned (regcache, E_V0_REGNUM,
+				    extract_unsigned_integer (valbuf, len,
+							      byte_order));
   else if (len <= 2 * v850_reg_size)
     {
       int i, regnum = E_V0_REGNUM;
@@ -1186,7 +1529,7 @@ v850_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
 {
   *size = kind;
 
-    switch (gdbarch_bfd_arch_info (gdbarch)->mach)
+  switch (gdbarch_bfd_arch_info (gdbarch)->mach)
     {
     case bfd_mach_v850e2:
     case bfd_mach_v850e2v3:
@@ -1295,10 +1638,9 @@ v850_frame_cache (frame_info_ptr this_frame, void **this_cache)
   return cache;
 }
 
-
 static struct value *
-v850_frame_prev_register (frame_info_ptr this_frame,
-			  void **this_cache, int regnum)
+v850_frame_prev_register (frame_info_ptr this_frame, void **this_cache,
+			  int regnum)
 {
   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
 
@@ -1317,18 +1659,18 @@ v850_frame_this_id (frame_info_ptr this_frame, void **this_cache,
   if (cache->base == 0)
     return;
 
-  *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr (), cache->pc);
+  *this_id
+    = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr (), cache->pc);
 }
 
-static const struct frame_unwind v850_frame_unwind = {
-  "v850 prologue",
-  NORMAL_FRAME,
-  default_frame_unwind_stop_reason,
-  v850_frame_this_id,
-  v850_frame_prev_register,
-  NULL,
-  default_frame_sniffer
-};
+static const struct frame_unwind v850_frame_unwind
+  = { "v850 prologue",
+      NORMAL_FRAME,
+      default_frame_unwind_stop_reason,
+      v850_frame_this_id,
+      v850_frame_prev_register,
+      NULL,
+      default_frame_sniffer };
 
 static CORE_ADDR
 v850_frame_base_address (frame_info_ptr this_frame, void **this_cache)
@@ -1338,12 +1680,9 @@ v850_frame_base_address (frame_info_ptr this_frame, void **this_cache)
   return cache->base;
 }
 
-static const struct frame_base v850_frame_base = {
-  &v850_frame_unwind,
-  v850_frame_base_address,
-  v850_frame_base_address,
-  v850_frame_base_address
-};
+static const struct frame_base v850_frame_base
+  = { &v850_frame_unwind, v850_frame_base_address, v850_frame_base_address,
+      v850_frame_base_address };
 
 static struct gdbarch *
 v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
@@ -1363,11 +1702,9 @@ v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
       e_machine = 0;
     }
 
-
   /* Try to find the architecture in the list of already defined
      architectures.  */
-  for (arches = gdbarch_list_lookup_by_info (arches, &info);
-       arches != NULL;
+  for (arches = gdbarch_list_lookup_by_info (arches, &info); arches != NULL;
        arches = gdbarch_list_lookup_by_info (arches->next, &info))
     {
       v850_gdbarch_tdep *tdep
@@ -1461,6 +1798,7 @@ v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 }
 
 void _initialize_v850_tdep ();
+
 void
 _initialize_v850_tdep ()
 {