gdb: fix gdbarch_tdep ODR violation

I would like to be able to use non-trivial types in gdbarch_tdep types.
This is not possible at the moment (in theory), because of the one
definition rule.

To allow it, rename all gdbarch_tdep types to <arch>_gdbarch_tdep, and
make them inherit from a gdbarch_tdep base class.  The inheritance is
necessary to be able to pass pointers to all these <arch>_gdbarch_tdep
objects to gdbarch_alloc, which takes a pointer to gdbarch_tdep.

These objects are never deleted through a base class pointer, so I
didn't include a virtual destructor.  In the future, if gdbarch objects
deletable, I could imagine that the gdbarch_tdep objects could become
owned by the gdbarch objects, and then it would become useful to have a
virtual destructor (so that the gdbarch object can delete the owned
gdbarch_tdep object).  But that's not necessary right now.

It turns out that RISC-V already has a gdbarch_tdep that is
non-default-constructible, so that provides a good motivation for this
change.

Most changes are fairly straightforward, mostly needing to add some
casts all over the place.  There is however the xtensa architecture,
doing its own little weird thing to define its gdbarch_tdep.  I did my
best to adapt it, but I can't test those changes.

Change-Id: Ic001903f91ddd106bd6ca09a79dabe8df2d69f3b

1 files changed, 15 insertions, 15 deletions

diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h
index e7f6837..b899cfd 100644
--- a/gdb/mips-tdep.h
+++ b/gdb/mips-tdep.h
@@ -83,39 +83,39 @@ enum mips_fpu_type
 };
 
 /* MIPS specific per-architecture information.  */
-struct gdbarch_tdep
+struct mips_gdbarch_tdep : gdbarch_tdep
 {
   /* from the elf header */
-  int elf_flags;
+  int elf_flags = 0;
 
   /* mips options */
-  enum mips_abi mips_abi;
-  enum mips_abi found_abi;
-  enum mips_isa mips_isa;
-  enum mips_fpu_type mips_fpu_type;
-  int mips_last_arg_regnum;
-  int mips_last_fp_arg_regnum;
-  int default_mask_address_p;
+  enum mips_abi mips_abi {};
+  enum mips_abi found_abi {};
+  enum mips_isa mips_isa {};
+  enum mips_fpu_type mips_fpu_type {};
+  int mips_last_arg_regnum = 0;
+  int mips_last_fp_arg_regnum = 0;
+  int default_mask_address_p = 0;
   /* Is the target using 64-bit raw integer registers but only
      storing a left-aligned 32-bit value in each?  */
-  int mips64_transfers_32bit_regs_p;
+  int mips64_transfers_32bit_regs_p = 0;
   /* Indexes for various registers.  IRIX and embedded have
      different values.  This contains the "public" fields.  Don't
      add any that do not need to be public.  */
-  const struct mips_regnum *regnum;
+  const struct mips_regnum *regnum = nullptr;
   /* Register names table for the current register set.  */
-  const char * const *mips_processor_reg_names;
+  const char * const *mips_processor_reg_names = nullptr;
 
   /* The size of register data available from the target, if known.
      This doesn't quite obsolete the manual
      mips64_transfers_32bit_regs_p, since that is documented to force
      left alignment even for big endian (very strange).  */
-  int register_size_valid_p;
-  int register_size;
+  int register_size_valid_p = 0;
+  int register_size = 0;
 
   /* Return the expected next PC if FRAME is stopped at a syscall
      instruction.  */
-  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr;
 };
 
 /* Register numbers of various important registers.  */