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| author | Feiyang Chen <chenfeiyang@loongson.cn> | 2022-08-02 17:16:56 +0800 |
|---|---|---|
| committer | Tiezhu Yang <yangtiezhu@loongson.cn> | 2022-08-09 22:22:23 +0800 |
| commit | ea3352172ec868b821fa34b31ba8128bde735405 (patch) | |
| tree | 60452294ef7a7f9524a174b0c5fa1f2ddd5ac7b0 /gdb/features | |
| parent | a88c79b77036e4778e70d62081c3cfd1044bb8e3 (diff) | |
| download | fsf-binutils-gdb-ea3352172ec868b821fa34b31ba8128bde735405.zip fsf-binutils-gdb-ea3352172ec868b821fa34b31ba8128bde735405.tar.gz fsf-binutils-gdb-ea3352172ec868b821fa34b31ba8128bde735405.tar.bz2 | |
gdb/gdbserver: LoongArch: Improve implementation of fcc registers
The current implementation of the fcc register is referenced to the
user_fp_state structure of the kernel uapi [1].
struct user_fp_state {
uint64_t fpr[32];
uint64_t fcc;
uint32_t fcsr;
};
But it is mistakenly defined as a 64-bit fputype register, resulting
in a confusing output of "info register".
(gdb) info register
...
fcc {f = 0x0, d = 0x0} {f = 0, d = 0}
...
According to "Condition Flag Register" in "LoongArch Reference Manual"
[2], there are 8 condition flag registers of size 1. Use 8 registers of
uint8 to make it easier for users to view the fcc register groups.
(gdb) info register
...
fcc0 0x1 1
fcc1 0x0 0
fcc2 0x0 0
fcc3 0x0 0
fcc4 0x0 0
fcc5 0x0 0
fcc6 0x0 0
fcc7 0x0 0
...
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h
[2] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_condition_flag_register
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Diffstat (limited to 'gdb/features')
| -rw-r--r-- | gdb/features/loongarch/fpu.c | 9 | ||||
| -rw-r--r-- | gdb/features/loongarch/fpu.xml | 9 |
2 files changed, 16 insertions, 2 deletions
diff --git a/gdb/features/loongarch/fpu.c b/gdb/features/loongarch/fpu.c index ea3e1dd..183ed54 100644 --- a/gdb/features/loongarch/fpu.c +++ b/gdb/features/loongarch/fpu.c @@ -49,7 +49,14 @@ create_feature_loongarch_fpu (struct target_desc *result, long regnum) tdesc_create_reg (feature, "f29", regnum++, 1, "float", 64, "fputype"); tdesc_create_reg (feature, "f30", regnum++, 1, "float", 64, "fputype"); tdesc_create_reg (feature, "f31", regnum++, 1, "float", 64, "fputype"); - tdesc_create_reg (feature, "fcc", regnum++, 1, "float", 64, "fputype"); + tdesc_create_reg (feature, "fcc0", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc1", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc2", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc3", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc4", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc5", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc6", regnum++, 1, "float", 8, "uint8"); + tdesc_create_reg (feature, "fcc7", regnum++, 1, "float", 8, "uint8"); tdesc_create_reg (feature, "fcsr", regnum++, 1, "float", 32, "uint32"); return regnum; } diff --git a/gdb/features/loongarch/fpu.xml b/gdb/features/loongarch/fpu.xml index a61057e..e81e338 100644 --- a/gdb/features/loongarch/fpu.xml +++ b/gdb/features/loongarch/fpu.xml @@ -45,6 +45,13 @@ <reg name="f29" bitsize="64" type="fputype" group="float"/> <reg name="f30" bitsize="64" type="fputype" group="float"/> <reg name="f31" bitsize="64" type="fputype" group="float"/> - <reg name="fcc" bitsize="64" type="fputype" group="float"/> + <reg name="fcc0" bitsize="8" type="uint8" group="float"/> + <reg name="fcc1" bitsize="8" type="uint8" group="float"/> + <reg name="fcc2" bitsize="8" type="uint8" group="float"/> + <reg name="fcc3" bitsize="8" type="uint8" group="float"/> + <reg name="fcc4" bitsize="8" type="uint8" group="float"/> + <reg name="fcc5" bitsize="8" type="uint8" group="float"/> + <reg name="fcc6" bitsize="8" type="uint8" group="float"/> + <reg name="fcc7" bitsize="8" type="uint8" group="float"/> <reg name="fcsr" bitsize="32" type="uint32" group="float"/> </feature> |