Initial creation of sourceware repositorygdb-4_18-branchpoint

63 files changed, 1947 insertions, 0 deletions

diff --git a/gdb/config/mips/bigmips.mt b/gdb/config/mips/bigmips.mt
new file mode 100644
index 0000000..38f03f2
--- /dev/null
+++ b/gdb/config/mips/bigmips.mt
@@ -0,0 +1,3 @@
+# Target: Big-endian MIPS machine such as Sony News
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-bigmips.h
diff --git a/gdb/config/mips/bigmips64.mt b/gdb/config/mips/bigmips64.mt
new file mode 100644
index 0000000..fcb7b21
--- /dev/null
+++ b/gdb/config/mips/bigmips64.mt
@@ -0,0 +1,3 @@
+# Target: Big-endian MIPS machine such as Sony News
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-bigmips64.h
diff --git a/gdb/config/mips/decstation.mh b/gdb/config/mips/decstation.mh
new file mode 100644
index 0000000..da417b2
--- /dev/null
+++ b/gdb/config/mips/decstation.mh
@@ -0,0 +1,5 @@
+# Host: Little-endian MIPS machine such as DECstation.
+XDEPFILES= 
+XM_FILE= xm-mips.h
+NAT_FILE= nm-mips.h
+NATDEPFILES= infptrace.o inftarg.o corelow.o mips-nat.o fork-child.o
diff --git a/gdb/config/mips/decstation.mt b/gdb/config/mips/decstation.mt
new file mode 100644
index 0000000..1984722
--- /dev/null
+++ b/gdb/config/mips/decstation.mt
@@ -0,0 +1,3 @@
+# Target: Little-endian MIPS machine such as DECstation.
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-mips.h
diff --git a/gdb/config/mips/embed.mt b/gdb/config/mips/embed.mt
new file mode 100644
index 0000000..42ab4aa
--- /dev/null
+++ b/gdb/config/mips/embed.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o remote-array.o
+TM_FILE= tm-embed.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/embed64.mt b/gdb/config/mips/embed64.mt
new file mode 100644
index 0000000..ed60fd2
--- /dev/null
+++ b/gdb/config/mips/embed64.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o remote-array.o
+TM_FILE= tm-embed64.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/embedl.mt b/gdb/config/mips/embedl.mt
new file mode 100644
index 0000000..0ed8b8d
--- /dev/null
+++ b/gdb/config/mips/embedl.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o remote-array.o
+TM_FILE= tm-embedl.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/embedl64.mt b/gdb/config/mips/embedl64.mt
new file mode 100644
index 0000000..28c41be
--- /dev/null
+++ b/gdb/config/mips/embedl64.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o remote-array.o
+TM_FILE= tm-embedl64.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/irix3.mh b/gdb/config/mips/irix3.mh
new file mode 100644
index 0000000..311d697
--- /dev/null
+++ b/gdb/config/mips/irix3.mh
@@ -0,0 +1,6 @@
+# Host: SGI Iris running irix 3.x
+XDEPFILES= 
+XM_FILE= xm-irix3.h
+NAT_FILE= nm-irix3.h
+NATDEPFILES= fork-child.o corelow.o infptrace.o inftarg.o mips-nat.o
+XM_CLIBS=-lbsd
diff --git a/gdb/config/mips/irix3.mt b/gdb/config/mips/irix3.mt
new file mode 100644
index 0000000..b3fa4dd
--- /dev/null
+++ b/gdb/config/mips/irix3.mt
@@ -0,0 +1,3 @@
+# Target: MIPS SGI running Irix 3
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-irix3.h
diff --git a/gdb/config/mips/irix4.mh b/gdb/config/mips/irix4.mh
new file mode 100644
index 0000000..68511e6
--- /dev/null
+++ b/gdb/config/mips/irix4.mh
@@ -0,0 +1,8 @@
+# Host: SGI Iris running irix 4.x
+XDEPFILES= ser-tcp.o
+XM_FILE= xm-irix4.h
+NAT_FILE= nm-irix4.h
+NATDEPFILES= fork-child.o procfs.o irix4-nat.o corelow.o
+XM_CLIBS=-lbsd -lsun
+# use cc in K&R mode, bump up some static compiler tables.
+CC = cc -cckr -Wf,-XNg1500 -Wf,-XNk1000 -Wf,-XNh1100
diff --git a/gdb/config/mips/irix5.mh b/gdb/config/mips/irix5.mh
new file mode 100644
index 0000000..0e27686
--- /dev/null
+++ b/gdb/config/mips/irix5.mh
@@ -0,0 +1,6 @@
+# Host: SGI Iris running irix 5.x
+XDEPFILES= ser-tcp.o
+XM_FILE= xm-irix5.h
+NAT_FILE= nm-irix5.h
+NATDEPFILES= fork-child.o procfs.o irix5-nat.o corelow.o
+XM_CLIBS=-lbsd -lsun
diff --git a/gdb/config/mips/irix5.mt b/gdb/config/mips/irix5.mt
new file mode 100644
index 0000000..5b17bcd
--- /dev/null
+++ b/gdb/config/mips/irix5.mt
@@ -0,0 +1,3 @@
+# Target: MIPS SGI running Irix 5
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-irix5.h
diff --git a/gdb/config/mips/littlemips.mh b/gdb/config/mips/littlemips.mh
new file mode 100644
index 0000000..103919d
--- /dev/null
+++ b/gdb/config/mips/littlemips.mh
@@ -0,0 +1,3 @@
+# Host: Little-endian MIPS machine such as DECstation.
+XDEPFILES= infptrace.o inftarg.o fork-child.o corelow.o core-aout.o
+XM_FILE= xm-mips.h
diff --git a/gdb/config/mips/littlemips.mt b/gdb/config/mips/littlemips.mt
new file mode 100644
index 0000000..1984722
--- /dev/null
+++ b/gdb/config/mips/littlemips.mt
@@ -0,0 +1,3 @@
+# Target: Little-endian MIPS machine such as DECstation.
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-mips.h
diff --git a/gdb/config/mips/mipsm3.mh b/gdb/config/mips/mipsm3.mh
new file mode 100644
index 0000000..e049d68
--- /dev/null
+++ b/gdb/config/mips/mipsm3.mh
@@ -0,0 +1,7 @@
+# Host: Little endian MIPS machine such as pmax
+# running Mach 3.0 operating system
+
+XDEPFILES= core-aout.o
+NATDEPFILES= mipsm3-nat.o m3-nat.o
+XM_FILE= xm-mipsm3.h
+NAT_FILE= ../nm-m3.h
diff --git a/gdb/config/mips/mipsm3.mt b/gdb/config/mips/mipsm3.mt
new file mode 100644
index 0000000..66856d1
--- /dev/null
+++ b/gdb/config/mips/mipsm3.mt
@@ -0,0 +1,4 @@
+# Target: Little-endian MIPS machine such as pmax
+# running Mach 3.0 operating system
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-mipsm3.h
diff --git a/gdb/config/mips/mipsv4.mh b/gdb/config/mips/mipsv4.mh
new file mode 100644
index 0000000..87cb7e4
--- /dev/null
+++ b/gdb/config/mips/mipsv4.mh
@@ -0,0 +1,4 @@
+# Host: Mips running SVR4
+XM_FILE= xm-mipsv4.h
+NAT_FILE= ../nm-sysv4.h
+NATDEPFILES= fork-child.o procfs.o mipsv4-nat.o corelow.o core-regset.o solib.o
diff --git a/gdb/config/mips/mipsv4.mt b/gdb/config/mips/mipsv4.mt
new file mode 100644
index 0000000..6d3b47d
--- /dev/null
+++ b/gdb/config/mips/mipsv4.mt
@@ -0,0 +1,3 @@
+# Target: MIPS running SVR4
+TDEPFILES= mips-tdep.o
+TM_FILE= tm-mipsv4.h
diff --git a/gdb/config/mips/news-mips.mh b/gdb/config/mips/news-mips.mh
new file mode 100644
index 0000000..620fbaa
--- /dev/null
+++ b/gdb/config/mips/news-mips.mh
@@ -0,0 +1,4 @@
+# Host: Big-endian MIPS machine such as Sony News
+NATDEPFILES= infptrace.o inftarg.o fork-child.o corelow.o mips-nat.o
+XM_FILE= xm-news-mips.h
+NAT_FILE= nm-news-mips.h
diff --git a/gdb/config/mips/nm-irix3.h b/gdb/config/mips/nm-irix3.h
new file mode 100644
index 0000000..3f4b064
--- /dev/null
+++ b/gdb/config/mips/nm-irix3.h
@@ -0,0 +1,37 @@
+/* Definitions for SGI irix3 native support.
+   Copyright 1991, 1992 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* Don't need special routines for Irix v3 -- we can use infptrace.c */
+#undef FETCH_INFERIOR_REGISTERS
+
+#define U_REGS_OFFSET 0
+
+/* Figure out where the longjmp will land.  We expect that we have just entered
+   longjmp and haven't yet setup the stack frame, so the args are still in the
+   argument regs.  a0 (CALL_ARG0) points at the jmp_buf structure from which we
+   extract the pc (JB_PC) that we will land at.  The pc is copied into ADDR.
+   This routine returns true on success */
+
+#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
+extern int get_longjmp_target PARAMS ((CORE_ADDR *));
+
+/* Is this really true or is this just a leftover from a DECstation
+   config file?  */
+
+#define	ONE_PROCESS_WRITETEXT
diff --git a/gdb/config/mips/nm-irix4.h b/gdb/config/mips/nm-irix4.h
new file mode 100644
index 0000000..017695c
--- /dev/null
+++ b/gdb/config/mips/nm-irix4.h
@@ -0,0 +1,61 @@
+/* Definitions for native support of irix4.
+
+Copyright (C) 1991, 1992 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/*
+ * Let's use /debug instead of all this dangerous mucking about
+ * with ptrace(), which seems *extremely* fragile, anyway.
+ */
+#define USE_PROC_FS
+#define CTL_PROC_NAME_FMT "/debug/%d"
+#define AS_PROC_NAME_FMT "/debug/%d"
+#define MAP_PROC_NAME_FMT "/debug/%d"
+#define STATUS_PROC_NAME_FMT "/debug/%d"
+
+/* Don't need special routines for the SGI -- we can use infptrace.c */
+#undef FETCH_INFERIOR_REGISTERS
+
+#define U_REGS_OFFSET 0
+
+/* Is this really true or is this just a leftover from a DECstation
+   config file?  */
+
+#define	ONE_PROCESS_WRITETEXT
+
+#define TARGET_HAS_HARDWARE_WATCHPOINTS
+
+/* Temporary new watchpoint stuff */
+#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
+	((type) == bp_hardware_watchpoint)
+
+/* When a hardware watchpoint fires off the PC will be left at the
+   instruction which caused the watchpoint.  It will be necessary for
+   GDB to step over the watchpoint. */
+
+#define STOPPED_BY_WATCHPOINT(W) \
+  procfs_stopped_by_watchpoint(inferior_pid)
+extern int procfs_stopped_by_watchpoint PARAMS ((int));
+
+#define HAVE_NONSTEPPABLE_WATCHPOINT
+
+/* Use these macros for watchpoint insertion/deletion.  */
+/* type can be 0: write watch, 1: read watch, 2: access watch (read/write) */
+#define target_insert_watchpoint(addr, len, type) procfs_set_watchpoint (inferior_pid, addr, len, 2)
+#define target_remove_watchpoint(addr, len, type) procfs_set_watchpoint (inferior_pid, addr, 0, 0)
+extern int procfs_set_watchpoint PARAMS ((int, CORE_ADDR, int, int));
diff --git a/gdb/config/mips/nm-irix5.h b/gdb/config/mips/nm-irix5.h
new file mode 100644
index 0000000..90d454b
--- /dev/null
+++ b/gdb/config/mips/nm-irix5.h
@@ -0,0 +1,44 @@
+/* Definitions for native support of irix5.
+
+Copyright (C) 1993, 1998 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "nm-sysv4.h"
+#undef IN_SOLIB_DYNSYM_RESOLVE_CODE
+
+#define TARGET_HAS_HARDWARE_WATCHPOINTS
+
+/* Temporary new watchpoint stuff */
+#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
+	((type) == bp_hardware_watchpoint)
+
+/* When a hardware watchpoint fires off the PC will be left at the
+   instruction which caused the watchpoint.  It will be necessary for
+   GDB to step over the watchpoint. */
+
+#define STOPPED_BY_WATCHPOINT(W) \
+  procfs_stopped_by_watchpoint(inferior_pid)
+extern int procfs_stopped_by_watchpoint PARAMS ((int));
+
+#define HAVE_NONSTEPPABLE_WATCHPOINT
+
+/* Use these macros for watchpoint insertion/deletion.  */
+/* type can be 0: write watch, 1: read watch, 2: access watch (read/write) */
+#define target_insert_watchpoint(addr, len, type) procfs_set_watchpoint (inferior_pid, addr, len, 2)
+#define target_remove_watchpoint(addr, len, type) procfs_set_watchpoint (inferior_pid, addr, 0, 0)
+extern int procfs_set_watchpoint PARAMS ((int, CORE_ADDR, int, int));
diff --git a/gdb/config/mips/nm-mips.h b/gdb/config/mips/nm-mips.h
new file mode 100644
index 0000000..6418b86
--- /dev/null
+++ b/gdb/config/mips/nm-mips.h
@@ -0,0 +1,32 @@
+/* Native definitions for GDB on DECstations, Sony News. and MIPS Riscos systems
+   Copyright (C) 1986, 1987, 1989, 1992 Free Software Foundation, Inc.
+   Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin(af@cs.cmu.edu) at CMU
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* Override copies of {fetch,store}_inferior_registers in infptrace.c.  */
+#define FETCH_INFERIOR_REGISTERS
+
+/* Figure out where the longjmp will land.  We expect that we have just entered
+   longjmp and haven't yet setup the stack frame, so the args are still in the
+   argument regs.  a0 (CALL_ARG0) points at the jmp_buf structure from which we
+   extract the pc (JB_PC) that we will land at.  The pc is copied into ADDR.
+   This routine returns true on success */
+
+#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
+extern int get_longjmp_target PARAMS ((CORE_ADDR *));
diff --git a/gdb/config/mips/nm-news-mips.h b/gdb/config/mips/nm-news-mips.h
new file mode 100644
index 0000000..1ab63ba
--- /dev/null
+++ b/gdb/config/mips/nm-news-mips.h
@@ -0,0 +1,42 @@
+/* Definitions to make GDB run on a mips box under 4.3bsd.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+   Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin(af@cs.cmu.edu) at CMU
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef NM_NEWS_MIPS_H
+#define NM_NEWS_MIPS_H 1
+
+/* Needed for RISC NEWS core files.  */
+#include <machine/machparam.h>
+#include <sys/types.h>
+#define KERNEL_U_ADDR UADDR
+
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+	if (regno < 38) addr = (NBPG*UPAGES) + (regno - 38)*sizeof(int);\
+	else addr = 0; /* ..somewhere in the pcb */
+
+/* Kernel is a bit tenacious about sharing text segments, disallowing bpts.  */
+#define	ONE_PROCESS_WRITETEXT
+
+#include "mips/nm-mips.h"
+
+/* Apparently not in <sys/types.h> */
+typedef int pid_t;
+
+#endif	/* NM_NEWS_MIPS_H */
diff --git a/gdb/config/mips/nm-riscos.h b/gdb/config/mips/nm-riscos.h
new file mode 100644
index 0000000..2d54345
--- /dev/null
+++ b/gdb/config/mips/nm-riscos.h
@@ -0,0 +1,59 @@
+/* This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* MIPS running RISC/os 4.52C.  */
+
+#define PCB_OFFSET(FIELD) ((int)&((struct user*)0)->u_pcb.FIELD)
+
+/* RISC/os 5.0 defines this in machparam.h.  */
+#include <bsd43/machine/machparam.h>
+#define NBPG BSD43_NBPG
+#define UPAGES BSD43_UPAGES
+
+/* Where is this used?  I don't see any uses in mips-nat.c, and I don't think
+   the uses in infptrace.c are used if FETCH_INFERIOR_REGISTERS is defined.
+   Does the compiler react badly to "extern CORE_ADDR kernel_u_addr" (even
+   if never referenced)?  */
+#define KERNEL_U_ADDR BSD43_UADDR
+
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+	      if (regno < FP0_REGNUM) \
+		  addr =  UPAGES*NBPG-EF_SIZE+4*((regno)+EF_AT-1); \
+	      else if (regno < PC_REGNUM) \
+		  addr = PCB_OFFSET(pcb_fpregs[0]) + 4*(regno-FP0_REGNUM); \
+              else if (regno == PS_REGNUM) \
+                  addr = UPAGES*NBPG-EF_SIZE+4*EF_SR; \
+              else if (regno == BADVADDR_REGNUM) \
+  		  addr = UPAGES*NBPG-EF_SIZE+4*EF_BADVADDR; \
+	      else if (regno == LO_REGNUM) \
+		  addr = UPAGES*NBPG-EF_SIZE+4*EF_MDLO; \
+	      else if (regno == HI_REGNUM) \
+		  addr = UPAGES*NBPG-EF_SIZE+4*EF_MDHI; \
+	      else if (regno == CAUSE_REGNUM) \
+		  addr = UPAGES*NBPG-EF_SIZE+4*EF_CAUSE; \
+	      else if (regno == PC_REGNUM) \
+		  addr = UPAGES*NBPG-EF_SIZE+4*EF_EPC; \
+              else if (regno < FCRCS_REGNUM) \
+		  addr = PCB_OFFSET(pcb_fpregs[0]) + 4*(regno-FP0_REGNUM); \
+	      else if (regno == FCRCS_REGNUM) \
+		  addr = PCB_OFFSET(pcb_fpc_csr); \
+	      else if (regno == FCRIR_REGNUM) \
+		  addr = PCB_OFFSET(pcb_fpc_eir); \
+              else \
+                  addr = 0;
+
+#include "mips/nm-mips.h"
+
+/* Override copies of {fetch,store}_inferior_registers in infptrace.c.  */
+#define FETCH_INFERIOR_REGISTERS
diff --git a/gdb/config/mips/riscos.mh b/gdb/config/mips/riscos.mh
new file mode 100644
index 0000000..6a3192f
--- /dev/null
+++ b/gdb/config/mips/riscos.mh
@@ -0,0 +1,16 @@
+# Host: MIPS running RISC/os
+
+XM_FILE= xm-riscos.h
+
+NAT_FILE= nm-riscos.h
+NATDEPFILES= infptrace.o inftarg.o fork-child.o corelow.o mips-nat.o
+
+MH_CFLAGS=-Wf,-XNh10000
+
+# ptrace(2) apparently has problems in the BSD environment.  No workaround is
+# known except to select the sysv environment.  Could we use /proc instead?
+# These "sysv environments" and "bsd environments" often end up being a pain.
+#
+# This is not part of CFLAGS because perhaps not all C compilers have this
+# option.
+CC= cc -systype sysv
diff --git a/gdb/config/mips/tm-bigmips.h b/gdb/config/mips/tm-bigmips.h
new file mode 100644
index 0000000..271ceb0
--- /dev/null
+++ b/gdb/config/mips/tm-bigmips.h
@@ -0,0 +1,21 @@
+/* Copyright (C) 1990 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_DEFAULT BIG_ENDIAN
+
+#include "mips/tm-mips.h"
diff --git a/gdb/config/mips/tm-bigmips64.h b/gdb/config/mips/tm-bigmips64.h
new file mode 100644
index 0000000..8b255a5
--- /dev/null
+++ b/gdb/config/mips/tm-bigmips64.h
@@ -0,0 +1,23 @@
+/* Target machine parameters for MIPS r4000
+   Copyright 1994 Free Software Foundation, Inc.
+   Contributed by Ian Lance Taylor (ian@cygnus.com)
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_DEFAULT BIG_ENDIAN
+
+#include "mips/tm-mips64.h"
diff --git a/gdb/config/mips/tm-embed.h b/gdb/config/mips/tm-embed.h
new file mode 100644
index 0000000..7bf1759
--- /dev/null
+++ b/gdb/config/mips/tm-embed.h
@@ -0,0 +1,49 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+
+#include "mips/tm-bigmips.h"
+
+#undef DEFAULT_MIPS_TYPE
+#define DEFAULT_MIPS_TYPE "r3051"
+
+/* Watchpoint support */
+
+#define TARGET_HAS_HARDWARE_WATCHPOINTS
+
+/* Use these macros for watchpoint insertion/deletion.  */
+/* type can be 0: write watch, 1: read watch, 2: access watch (read/write) */
+
+#define target_insert_watchpoint(addr, len, type) \
+	remote_mips_set_watchpoint (addr, len, type)
+int remote_mips_set_watchpoint PARAMS ((CORE_ADDR addr, int len, int type));
+
+#define target_remove_watchpoint(addr, len, type) \
+	remote_mips_remove_watchpoint (addr, len, type)
+int remote_mips_remove_watchpoint PARAMS ((CORE_ADDR addr, int len, int type));
+
+/* We need to remove watchpoints when stepping, else we hit them again! */
+
+#define HAVE_NONSTEPPABLE_WATCHPOINT
+
+#define STOPPED_BY_WATCHPOINT(w) remote_mips_stopped_by_watchpoint ()
+
+#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
+  remote_mips_can_use_hardware_watchpoint(cnt)
+int remote_mips_can_use_hardware_watchpoint PARAMS ((int cnt));
diff --git a/gdb/config/mips/tm-embed64.h b/gdb/config/mips/tm-embed64.h
new file mode 100644
index 0000000..df90f58
--- /dev/null
+++ b/gdb/config/mips/tm-embed64.h
@@ -0,0 +1,21 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+
+#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-embedl.h b/gdb/config/mips/tm-embedl.h
new file mode 100644
index 0000000..23abcd9
--- /dev/null
+++ b/gdb/config/mips/tm-embedl.h
@@ -0,0 +1,21 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+
+#include "mips/tm-mips.h"
diff --git a/gdb/config/mips/tm-embedl64.h b/gdb/config/mips/tm-embedl64.h
new file mode 100644
index 0000000..c7dca19
--- /dev/null
+++ b/gdb/config/mips/tm-embedl64.h
@@ -0,0 +1,21 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+
+#include "mips/tm-mips64.h"
diff --git a/gdb/config/mips/tm-irix3.h b/gdb/config/mips/tm-irix3.h
new file mode 100644
index 0000000..7e8e53e
--- /dev/null
+++ b/gdb/config/mips/tm-irix3.h
@@ -0,0 +1,81 @@
+/* Target machine description for SGI Iris under Irix, for GDB.
+   Copyright 1990, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "mips/tm-bigmips.h"
+
+/* SGI's assembler doesn't grok dollar signs in identifiers.
+   So we use dots instead.  This item must be coordinated with G++. */
+#undef CPLUS_MARKER
+#define CPLUS_MARKER '.'
+
+/* Redefine register numbers for SGI. */
+
+#undef NUM_REGS
+#undef REGISTER_NAMES
+#undef FP0_REGNUM
+#undef PC_REGNUM
+#undef PS_REGNUM
+#undef HI_REGNUM
+#undef LO_REGNUM
+#undef CAUSE_REGNUM
+#undef BADVADDR_REGNUM
+#undef FCRCS_REGNUM
+#undef FCRIR_REGNUM
+
+/* Number of machine registers */
+
+#define NUM_REGS 71
+
+/* Initializer for an array of names of registers.
+   There should be NUM_REGS strings in this initializer.  */
+
+#define REGISTER_NAMES 	\
+    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
+	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
+	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
+	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"fp",	"ra", \
+	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
+	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
+	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
+	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
+	"pc",	"cause", "bad",	"hi",	"lo",	"fsr",  "fir" \
+    }
+
+/* Register numbers of various important registers.
+   Note that some of these values are "real" register numbers,
+   and correspond to the general registers of the machine,
+   and some are "phony" register numbers which are too large
+   to be actual register numbers as far as the user is concerned
+   but do serve to get the desired values when passed to read_register.  */
+
+#define FP0_REGNUM 32		/* Floating point register 0 (single float) */
+#define PC_REGNUM 64		/* Contains program counter */
+#define CAUSE_REGNUM 65		/* describes last exception */
+#define BADVADDR_REGNUM 66	/* bad vaddr for addressing exception */
+#define HI_REGNUM 67		/* Multiple/divide temp */
+#define LO_REGNUM 68		/* ... */
+#define FCRCS_REGNUM 69		/* FP control/status */
+#define FCRIR_REGNUM 70		/* FP implementation/revision */
+
+/* Offsets for register values in _sigtramp frame.
+   sigcontext is immediately above the _sigtramp frame on Irix.  */
+#define SIGFRAME_BASE		0x0 
+#define SIGFRAME_PC_OFF		(SIGFRAME_BASE + 2 * 4)
+#define SIGFRAME_REGSAVE_OFF	(SIGFRAME_BASE + 3 * 4)
+#define SIGFRAME_FPREGSAVE_OFF	(SIGFRAME_BASE + 3 * 4 + 32 * 4 + 4)
diff --git a/gdb/config/mips/tm-irix5.h b/gdb/config/mips/tm-irix5.h
new file mode 100644
index 0000000..ad98e88
--- /dev/null
+++ b/gdb/config/mips/tm-irix5.h
@@ -0,0 +1,75 @@
+/* Target machine description for SGI Iris under Irix 5, for GDB.
+   Copyright 1990, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "mips/tm-irix3.h"
+
+#if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
+/*
+ * Irix 6 (n32 ABI) has 32-bit GP regs and 64-bit FP regs
+ */
+
+#undef  REGISTER_BYTES
+#define REGISTER_BYTES (MIPS_NUMREGS * 8 + (NUM_REGS - MIPS_NUMREGS) * MIPS_REGSIZE)
+
+#undef  REGISTER_BYTE
+#define REGISTER_BYTE(N) \
+     (((N) < FP0_REGNUM) ? (N) * MIPS_REGSIZE : \
+      ((N) < FP0_REGNUM + 32) ?     \
+      FP0_REGNUM * MIPS_REGSIZE + \
+      ((N) - FP0_REGNUM) * sizeof(double) : \
+      32 * sizeof(double) + ((N) - 32) * MIPS_REGSIZE)
+
+#undef  REGISTER_VIRTUAL_TYPE
+#define REGISTER_VIRTUAL_TYPE(N) \
+	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_double \
+	 : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
+	 : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
+	 : builtin_type_int)
+
+#undef  MIPS_LAST_ARG_REGNUM
+#define MIPS_LAST_ARG_REGNUM 11  /* N32 uses R4 through R11 for args */
+
+#undef  MIPS_NUM_ARG_REGS
+#define MIPS_NUM_ARG_REGS 8
+
+#endif /* N32 */
+
+/* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
+   platform) $25 must hold the function address.  Dest_Reg is a macro
+   used in CALL_DUMMY in tm-mips.h.  */
+#undef Dest_Reg
+#define Dest_Reg 25
+
+/* The signal handler trampoline is called _sigtramp.  */
+#undef IN_SIGTRAMP
+#define IN_SIGTRAMP(pc, name) ((name) && STREQ ("_sigtramp", name))
+
+/* Irix 5 saves a full 64 bits for each register.  We skip 2 * 4 to
+   get to the saved PC (the register mask and status register are both
+   32 bits) and then another 4 to get to the lower 32 bits.  We skip
+   the same 4 bytes, plus the 8 bytes for the PC to get to the
+   registers, and add another 4 to get to the lower 32 bits.  We skip
+   8 bytes per register.  */
+#undef SIGFRAME_PC_OFF
+#define SIGFRAME_PC_OFF		(SIGFRAME_BASE + 2 * 4 + 4)
+#undef SIGFRAME_REGSAVE_OFF
+#define SIGFRAME_REGSAVE_OFF	(SIGFRAME_BASE + 2 * 4 + 8 + 4)
+#undef SIGFRAME_FPREGSAVE_OFF
+#define SIGFRAME_FPREGSAVE_OFF	(SIGFRAME_BASE + 2 * 4 + 8 + 32 * 8 + 4)
+#define SIGFRAME_REG_SIZE	8
diff --git a/gdb/config/mips/tm-mips.h b/gdb/config/mips/tm-mips.h
new file mode 100644
index 0000000..6a7091a
--- /dev/null
+++ b/gdb/config/mips/tm-mips.h
@@ -0,0 +1,560 @@
+/* Definitions to make GDB run on a mips box under 4.3bsd.
+   Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
+   Free Software Foundation, Inc.
+   Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin (af@cs.cmu.edu) at CMU..
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef TM_MIPS_H
+#define TM_MIPS_H 1
+
+#ifdef __STDC__
+struct frame_info;
+struct symbol;
+struct type;
+struct value;
+#endif
+
+#include <bfd.h>
+#include "coff/sym.h"		/* Needed for PDR below.  */
+#include "coff/symconst.h"
+
+#if !defined (TARGET_BYTE_ORDER_DEFAULT)
+#define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
+#endif
+
+#if !defined (GDB_TARGET_IS_MIPS64)
+#define GDB_TARGET_IS_MIPS64 0
+#endif
+
+#if !defined (MIPS_EABI)
+#define MIPS_EABI 0
+#endif
+
+#if !defined (TARGET_MONITOR_PROMPT)
+#define TARGET_MONITOR_PROMPT "<IDT>"
+#endif
+
+/* PC should be masked to remove possible MIPS16 flag */
+#if !defined (GDB_TARGET_MASK_DISAS_PC)
+#define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
+#endif
+#if !defined (GDB_TARGET_UNMASK_DISAS_PC)
+#define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
+#endif
+
+/* Floating point is IEEE compliant */
+#define IEEE_FLOAT
+
+/* The name of the usual type of MIPS processor that is in the target
+   system.  */
+
+#define DEFAULT_MIPS_TYPE "generic"
+
+/* Remove useless bits from an instruction address.  */
+
+#define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
+CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
+
+/* Remove useless bits from the stack pointer.  */
+
+#define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
+
+/* Offset from address of function to start of its code.
+   Zero on most machines.  */
+
+#define FUNCTION_START_OFFSET 0
+
+/* Advance PC across any function entry prologue instructions
+   to reach some "real" code.  */
+
+#define SKIP_PROLOGUE(pc)	pc = mips_skip_prologue (pc, 0)
+extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
+
+/* Return non-zero if PC points to an instruction which will cause a step
+   to execute both the instruction at PC and an instruction at PC+4.  */
+extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
+#define STEP_SKIPS_DELAY_P (1)
+#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
+
+/* Immediately after a function call, return the saved pc.
+   Can't always go through the frames for this because on some machines
+   the new frame is not set up until the new function executes
+   some instructions.  */
+
+#define SAVED_PC_AFTER_CALL(frame)	read_register(RA_REGNUM)
+
+/* Are we currently handling a signal */
+
+extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
+#define IN_SIGTRAMP(pc, name)	in_sigtramp(pc, name)
+
+/* Stack grows downward.  */
+
+#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
+
+#define BIG_ENDIAN 4321
+
+/* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
+   16- or 32-bit breakpoint should be used.  It returns a pointer
+   to a string of bytes that encode a breakpoint instruction, stores
+   the length of the string to *lenptr, and adjusts the pc (if necessary) to
+   point to the actual memory location where the breakpoint should be
+   inserted.  */
+
+extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
+#define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
+
+/* Amount PC must be decremented by after a breakpoint.
+   This is often the number of bytes in BREAKPOINT
+   but not always.  */
+
+#define DECR_PC_AFTER_BREAK 0
+
+/* Say how long (ordinary) registers are.  This is a piece of bogosity
+   used in push_word and a few other places; REGISTER_RAW_SIZE is the
+   real way to know how big a register is.  */
+
+#define REGISTER_SIZE 4
+
+/* The size of a register.  This is predefined in tm-mips64.h.  We
+   can't use REGISTER_SIZE because that is used for various other
+   things.  */
+
+#ifndef MIPS_REGSIZE
+#define MIPS_REGSIZE 4
+#endif
+
+/* The sizes of floating point registers.  */
+
+#define MIPS_FPU_SINGLE_REGSIZE 4
+#define MIPS_FPU_DOUBLE_REGSIZE 8
+
+/* Number of machine registers */
+
+#ifndef NUM_REGS
+#define NUM_REGS 90
+#endif
+
+/* Initializer for an array of names of registers.
+   There should be NUM_REGS strings in this initializer.  */
+
+#ifndef REGISTER_NAMES
+#define REGISTER_NAMES 	\
+    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
+	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
+	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
+	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
+	"sr",	"lo",	"hi",	"bad",	"cause","pc",    \
+	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
+	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
+	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
+	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
+	"fsr",  "fir",  "fp",	"", \
+	"",	"",	"",	"",	"",	"",	"",	"", \
+	"",	"",	"",	"",	"",	"",	"",	"", \
+    }
+#endif
+
+/* Register numbers of various important registers.
+   Note that some of these values are "real" register numbers,
+   and correspond to the general registers of the machine,
+   and some are "phony" register numbers which are too large
+   to be actual register numbers as far as the user is concerned
+   but do serve to get the desired values when passed to read_register.  */
+
+#define ZERO_REGNUM 0		/* read-only register, always 0 */
+#define V0_REGNUM 2		/* Function integer return value */
+#define A0_REGNUM 4		/* Loc of first arg during a subr call */
+#if MIPS_EABI
+#  define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
+#  define MIPS_NUM_ARG_REGS 8
+#else
+#  define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
+#  define MIPS_NUM_ARG_REGS 4
+#endif
+#define T9_REGNUM 25		/* Contains address of callee in PIC */
+#define SP_REGNUM 29		/* Contains address of top of stack */
+#define RA_REGNUM 31		/* Contains return address value */
+#define PS_REGNUM 32		/* Contains processor status */
+#define HI_REGNUM 34            /* Multiple/divide temp */
+#define LO_REGNUM 33            /* ... */
+#define BADVADDR_REGNUM 35	/* bad vaddr for addressing exception */
+#define CAUSE_REGNUM 36		/* describes last exception */
+#define PC_REGNUM 37		/* Contains program counter */
+#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
+#define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
+#if MIPS_EABI			/* EABI uses F12 through F19 for args */
+#  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
+#  define MIPS_NUM_FP_ARG_REGS 8
+#else				/* old ABI uses F12 through F15 for args */
+#  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
+#  define MIPS_NUM_FP_ARG_REGS 4
+#endif
+#define FCRCS_REGNUM 70         /* FP control/status */
+#define FCRIR_REGNUM 71         /* FP implementation/revision */
+#define FP_REGNUM 72		/* Pseudo register that contains true address of executing stack frame */
+#define	UNUSED_REGNUM 73	/* Never used, FIXME */
+#define	FIRST_EMBED_REGNUM 74	/* First CP0 register for embedded use */
+#define	PRID_REGNUM 89		/* Processor ID */
+#define	LAST_EMBED_REGNUM 89	/* Last one */
+
+/* Define DO_REGISTERS_INFO() to do machine-specific formatting
+   of register dumps. */
+
+#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
+extern void mips_do_registers_info PARAMS ((int, int));
+
+/* Total amount of space needed to store our copies of the machine's
+   register state, the array `registers'.  */
+
+#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
+
+/* Index within `registers' of the first byte of the space for
+   register N.  */
+
+#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
+
+/* Number of bytes of storage in the actual machine representation
+   for register N. */
+
+#define REGISTER_RAW_SIZE(N) REGISTER_VIRTUAL_SIZE(N)
+
+/* Number of bytes of storage in the program's representation
+   for register N. */
+
+#define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
+
+/* Largest value REGISTER_RAW_SIZE can have.  */
+
+#define MAX_REGISTER_RAW_SIZE 8
+
+/* Largest value REGISTER_VIRTUAL_SIZE can have.  */
+
+#define MAX_REGISTER_VIRTUAL_SIZE 8
+
+/* Return the GDB type object for the "standard" data type of data in
+   register N.  */
+
+#ifndef REGISTER_VIRTUAL_TYPE
+#define REGISTER_VIRTUAL_TYPE(N) \
+	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
+	 : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
+	 : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
+	 : builtin_type_int)
+#endif
+
+/* All mips targets store doubles in a register pair with the least
+   significant register in the lower numbered register.
+   If the target is big endian, double register values need conversion
+   between memory and register formats.  */
+
+#define REGISTER_CONVERT_TO_TYPE(n, type, buffer)			\
+  do {if (TARGET_BYTE_ORDER == BIG_ENDIAN				\
+	  && REGISTER_RAW_SIZE (n) == 4					\
+	  && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32			\
+	  && TYPE_CODE(type) == TYPE_CODE_FLT				\
+	  && TYPE_LENGTH(type) == 8) {					\
+        char __temp[4];							\
+	memcpy (__temp, ((char *)(buffer))+4, 4);			\
+	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
+	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
+
+#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)			\
+  do {if (TARGET_BYTE_ORDER == BIG_ENDIAN				\
+	  && REGISTER_RAW_SIZE (n) == 4					\
+	  && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32			\
+	  && TYPE_CODE(type) == TYPE_CODE_FLT				\
+	  && TYPE_LENGTH(type) == 8) {					\
+        char __temp[4];							\
+	memcpy (__temp, ((char *)(buffer))+4, 4);			\
+	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
+	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
+
+/* Store the address of the place in which to copy the structure the
+   subroutine will return.  Handled by mips_push_arguments.  */
+
+#define STORE_STRUCT_RETURN(addr, sp)	/**/
+
+/* Extract from an array REGBUF containing the (raw) register state
+   a function return value of type TYPE, and copy that, in virtual format,
+   into VALBUF.  XXX floats */
+
+#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
+  mips_extract_return_value(TYPE, REGBUF, VALBUF)
+extern void
+mips_extract_return_value PARAMS ((struct type *, char [], char *));
+
+/* Write into appropriate registers a function return value
+   of type TYPE, given in virtual format.  */
+
+#define STORE_RETURN_VALUE(TYPE,VALBUF) \
+  mips_store_return_value(TYPE, VALBUF)
+extern void mips_store_return_value PARAMS ((struct type *, char *));
+
+/* Extract from an array REGBUF containing the (raw) register state
+   the address in which a function should return its structure value,
+   as a CORE_ADDR (or an expression that can be used as one).  */
+/* The address is passed in a0 upon entry to the function, but when
+   the function exits, the compiler has copied the value to v0.  This
+   convention is specified by the System V ABI, so I think we can rely
+   on it.  */
+
+#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
+  (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
+		    REGISTER_RAW_SIZE (V0_REGNUM)))
+
+extern use_struct_convention_fn mips_use_struct_convention;
+#define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
+
+/* Describe the pointer in each stack frame to the previous stack frame
+   (its caller).  */
+
+/* FRAME_CHAIN takes a frame's nominal address
+   and produces the frame's chain-pointer. */
+
+#define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
+extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
+
+/* Define other aspects of the stack frame.  */
+
+
+/* A macro that tells us whether the function invocation represented
+   by FI does not have a frame on the stack associated with it.  If it
+   does not, FRAMELESS is set to 1, else 0.  */
+/* We handle this differently for mips, and maybe we should not */
+
+#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}
+
+/* Saved Pc.  */
+
+#define FRAME_SAVED_PC(FRAME)	(mips_frame_saved_pc(FRAME))
+extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
+
+#define FRAME_ARGS_ADDRESS(fi)	(fi)->frame
+
+#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
+
+/* Return number of args passed to a frame.
+   Can return -1, meaning no way to tell.  */
+
+#define FRAME_NUM_ARGS(num, fi)	(num = mips_frame_num_args(fi))
+extern int mips_frame_num_args PARAMS ((struct frame_info *));
+
+/* Return number of bytes at start of arglist that are not really args.  */
+
+#define FRAME_ARGS_SKIP 0
+
+/* Put here the code to store, into a struct frame_saved_regs,
+   the addresses of the saved registers of frame described by FRAME_INFO.
+   This includes special registers such as pc and fp saved in special
+   ways in the stack frame.  sp is even more special:
+   the address we return for it IS the sp for the next frame.  */
+
+#define FRAME_INIT_SAVED_REGS(frame_info) \
+  do { \
+    if ((frame_info)->saved_regs == NULL) \
+      mips_find_saved_regs (frame_info); \
+    (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
+  } while (0)
+extern void mips_find_saved_regs PARAMS ((struct frame_info *));
+
+
+/* Things needed for making the inferior call functions.  */
+
+/* Stack must be aligned on 32-bit boundaries when synthesizing
+   function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
+   handle it. */
+
+#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
+    sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))
+extern CORE_ADDR
+mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
+
+/* Push an empty stack frame, to record the current PC, etc.  */
+
+#define PUSH_DUMMY_FRAME 	mips_push_dummy_frame()
+extern void mips_push_dummy_frame PARAMS ((void));
+
+/* Discard from the stack the innermost frame, restoring all registers.  */
+
+#define POP_FRAME		mips_pop_frame()
+extern void mips_pop_frame PARAMS ((void));
+
+#define CALL_DUMMY { 0 }
+
+#define CALL_DUMMY_START_OFFSET (0)
+
+#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
+
+/* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
+   It doesn't hurt to do this on other systems; $t9 will be ignored.  */
+#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
+    write_register(T9_REGNUM, fun)
+
+#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
+
+#define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
+extern CORE_ADDR mips_call_dummy_address PARAMS ((void));
+
+/* There's a mess in stack frame creation.  See comments in blockframe.c
+   near reference to INIT_FRAME_PC_FIRST.  */
+
+#define	INIT_FRAME_PC(fromleaf, prev) /* nada */
+
+#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
+   mips_init_frame_pc_first(fromleaf, prev)
+extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
+
+/* Special symbol found in blocks associated with routines.  We can hang
+   mips_extra_func_info_t's off of this.  */
+
+#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
+extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
+
+/* Specific information about a procedure.
+   This overlays the MIPS's PDR records, 
+   mipsread.c (ab)uses this to save memory */
+
+typedef struct mips_extra_func_info {
+	long	numargs;	/* number of args to procedure (was iopt) */
+	bfd_vma high_addr;      /* upper address bound */
+	long	frame_adjust;	/* offset of FP from SP (used on MIPS16) */
+	PDR	pdr;		/* Procedure descriptor record */
+} *mips_extra_func_info_t;
+
+#define EXTRA_FRAME_INFO \
+  mips_extra_func_info_t proc_desc; \
+  int num_args;
+
+#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
+extern void init_extra_frame_info PARAMS ((struct frame_info *));
+
+#define	PRINT_EXTRA_FRAME_INFO(fi) \
+  { \
+    if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
+      printf_filtered (" frame pointer is at %s+%d\n", \
+                       REGISTER_NAME (fi->proc_desc->pdr.framereg), \
+                                 fi->proc_desc->pdr.frameoffset); \
+  }
+
+/* It takes two values to specify a frame on the MIPS.
+
+   In fact, the *PC* is the primary value that sets up a frame.  The
+   PC is looked up to see what function it's in; symbol information
+   from that function tells us which register is the frame pointer
+   base, and what offset from there is the "virtual frame pointer".
+   (This is usually an offset from SP.)  On most non-MIPS machines,
+   the primary value is the SP, and the PC, if needed, disambiguates
+   multiple functions with the same SP.  But on the MIPS we can't do
+   that since the PC is not stored in the same part of the frame every
+   time.  This does not seem to be a very clever way to set up frames,
+   but there is nothing we can do about that).  */
+
+#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
+extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
+
+/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
+
+#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
+
+/* Convert a ecoff register number to a gdb REGNUM */
+
+#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
+
+/* If the current gcc for for this target does not produce correct debugging
+   information for float parameters, both prototyped and unprototyped, then
+   define this macro.  This forces gdb to  always assume that floats are
+   passed as doubles and then converted in the callee.
+
+   For the mips chip, it appears that the debug info marks the parameters as
+   floats regardless of whether the function is prototyped, but the actual
+   values are passed as doubles for the non-prototyped case and floats for
+   the prototyped case.  Thus we choose to make the non-prototyped case work
+   for C and break the prototyped case, since the non-prototyped case is
+   probably much more common.  (FIXME). */
+
+#define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
+
+/* Select the default mips disassembler */
+
+#define TM_PRINT_INSN_MACH 0
+
+
+/* These are defined in mdebugread.c and are used in mips-tdep.c  */
+extern CORE_ADDR sigtramp_address, sigtramp_end;
+extern void fixup_sigtramp PARAMS ((void));
+
+/* Defined in mips-tdep.c and used in remote-mips.c */
+extern char *mips_read_processor_type PARAMS ((void));
+
+/* Functions for dealing with MIPS16 call and return stubs.  */
+#define IN_SOLIB_CALL_TRAMPOLINE(pc, name)	mips_in_call_stub (pc, name)
+#define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)	mips_in_return_stub (pc, name)
+#define SKIP_TRAMPOLINE_CODE(pc)		mips_skip_stub (pc)
+#define IGNORE_HELPER_CALL(pc)			mips_ignore_helper (pc)
+extern int mips_in_call_stub PARAMS ((CORE_ADDR pc,  char *name));
+extern int mips_in_return_stub PARAMS ((CORE_ADDR pc,  char *name));
+extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
+extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
+
+#ifndef TARGET_MIPS
+#define TARGET_MIPS
+#endif
+
+/* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
+#define MIPS_INSTLEN 4		/* Length of an instruction */
+#define MIPS16_INSTLEN 2	/* Length of an instruction on MIPS16*/
+#define MIPS_NUMREGS 32		/* Number of integer or float registers */
+typedef unsigned long t_inst;	/* Integer big enough to hold an instruction */
+
+/* MIPS16 function addresses are odd (bit 0 is set).  Here are some
+   macros to test, set, or clear bit 0 of addresses.  */
+#define IS_MIPS16_ADDR(addr)	 ((addr) & 1)
+#define MAKE_MIPS16_ADDR(addr)	 ((addr) | 1)
+#define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
+
+#endif	/* TM_MIPS_H */
+
+/* Macros for setting and testing a bit in a minimal symbol that
+   marks it as 16-bit function.  The MSB of the minimal symbol's
+   "info" field is used for this purpose. This field is already
+   being used to store the symbol size, so the assumption is
+   that the symbol size cannot exceed 2^31.
+
+   ELF_MAKE_MSYMBOL_SPECIAL
+			tests whether an ELF symbol is "special", i.e. refers
+			to a 16-bit function, and sets a "special" bit in a 
+			minimal symbol to mark it as a 16-bit function
+   MSYMBOL_IS_SPECIAL	tests the "special" bit in a minimal symbol
+   MSYMBOL_SIZE		returns the size of the minimal symbol, i.e.
+			the "info" field with the "special" bit masked out
+*/
+
+#define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
+ { \
+  if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
+    MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
+    SYMBOL_VALUE_ADDRESS (msym) |= 1; \
+  } \
+ }
+   
+#define MSYMBOL_IS_SPECIAL(msym) \
+  (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
+#define MSYMBOL_SIZE(msym) \
+  ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
diff --git a/gdb/config/mips/tm-mips64.h b/gdb/config/mips/tm-mips64.h
new file mode 100644
index 0000000..56a8927
--- /dev/null
+++ b/gdb/config/mips/tm-mips64.h
@@ -0,0 +1,54 @@
+/* Target machine parameters for MIPS r4000
+   Copyright 1994, 1996 Free Software Foundation, Inc.
+   Contributed by Ian Lance Taylor (ian@cygnus.com)
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define GDB_TARGET_IS_MIPS64 1
+
+/* Use eight byte registers.  */
+#define MIPS_REGSIZE 8
+
+/* define 8 byte register type */
+#define REGISTER_VIRTUAL_TYPE(N) \
+        (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_double \
+	 : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
+	 : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
+	 : builtin_type_long_long)
+
+/* Load double words in CALL_DUMMY.  */
+#define OP_LDFPR 065	/* ldc1 */
+#define OP_LDGPR 067	/* ld */
+
+#if defined(MIPS_EABI) && (MIPS_EABI != 0)
+/* Define sizes for 64-bit data types, allow specific targets to override
+   these values.  Doing so may violate the strict EABI, but it's necessary
+   for some MIPS III and MIPS IV machines that want 64bit longs, but 32bit
+   pointers.  */
+#ifndef TARGET_LONG_BIT
+#define TARGET_LONG_BIT      64
+#endif
+#ifndef TARGET_LONG_LONG_BIT
+#define TARGET_LONG_LONG_BIT 64
+#endif
+#ifndef TARGET_PTR_BIT
+#define TARGET_PTR_BIT       64
+#endif
+#endif /* MIPS_EABI */
+
+/* Get the basic MIPS definitions.  */
+#include "tm-mips.h"
diff --git a/gdb/config/mips/tm-mipsm3.h b/gdb/config/mips/tm-mipsm3.h
new file mode 100644
index 0000000..f736604
--- /dev/null
+++ b/gdb/config/mips/tm-mipsm3.h
@@ -0,0 +1,66 @@
+/* Definitions to make GDB run on a mips box under Mach 3.0
+   Copyright (C) 1992 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* Mach specific definitions for little endian mips (e.g. pmax)
+ * running Mach 3.0
+ *
+ * Author: Jukka Virtanen <jtv@hut.fi>
+ */
+
+/* Include common definitions for Mach3 systems */
+#include "nm-m3.h"
+
+/* Define offsets to access CPROC stack when it does not have
+ * a kernel thread.
+ */
+
+/* From mk/user/threads/mips/csw.s */
+#define SAVED_FP	(12*4)
+#define SAVED_PC	(13*4)
+#define SAVED_BYTES	(14*4)
+
+/* Using these, define our offsets to items strored in
+ * cproc_switch in csw.s
+ */
+#define MACHINE_CPROC_SP_OFFSET SAVED_BYTES
+#define MACHINE_CPROC_PC_OFFSET SAVED_PC
+#define MACHINE_CPROC_FP_OFFSET SAVED_FP
+
+/* Thread flavors used in setting the Trace state.
+ *
+ * In <mach/machine/thread_status.h>
+ */
+#define TRACE_FLAVOR		MIPS_EXC_STATE
+#define TRACE_FLAVOR_SIZE	MIPS_EXC_STATE_COUNT
+#define TRACE_SET(x,state)	((struct mips_exc_state *)state)->cause = EXC_SST;
+#define TRACE_CLEAR(x,state)	0
+
+/* Mach supports attach/detach */
+#define ATTACH_DETACH 1
+
+#include "mips/tm-mips.h"
+
+/* Address of end of user stack space.
+ * for MACH, see <machine/vmparam.h>
+ */
+#undef  STACK_END_ADDR
+#define STACK_END_ADDR USRSTACK
+
+/* Output registers in tabular format */
+#define TABULAR_REGISTER_OUTPUT
diff --git a/gdb/config/mips/tm-mipsv4.h b/gdb/config/mips/tm-mipsv4.h
new file mode 100644
index 0000000..dd7aaa1
--- /dev/null
+++ b/gdb/config/mips/tm-mipsv4.h
@@ -0,0 +1,45 @@
+/* Target machine description for MIPS running SVR4, for GDB.
+   Copyright 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "mips/tm-bigmips.h"
+#include "tm-sysv4.h"
+
+/* When calling functions on a MIPS SVR4 ABI compliant platform
+   $25 must hold the function address.  Dest_Reg is a macro
+   used in CALL_DUMMY in tm-mips.h.  */
+#undef Dest_Reg
+#define Dest_Reg 25
+
+/* The signal handler trampoline is called _sigtramp.  */
+#undef IN_SIGTRAMP
+#define IN_SIGTRAMP(pc, name) ((name) && STREQ ("_sigtramp", name))
+ 
+/* On entry to the signal handler trampoline, an ucontext is already
+   pushed on the stack. We can get at the saved registers via the
+   mcontext which is contained within the ucontext.  */
+#define SIGFRAME_BASE	0
+#define SIGFRAME_REGSAVE_OFF	(SIGFRAME_BASE + 40)
+#define SIGFRAME_PC_OFF		(SIGFRAME_BASE + 40 + 35 * 4)
+#define SIGFRAME_FPREGSAVE_OFF	(SIGFRAME_BASE + 40 + 36 * 4)
+
+/* Use the alternate method of determining valid frame chains. */
+#define FRAME_CHAIN_VALID(fp,fi) alternate_frame_chain_valid (fp, fi)
+
+/* Convert a DWARF register number to a gdb REGNUM.  */
+#define DWARF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
diff --git a/gdb/config/mips/tm-tx39.h b/gdb/config/mips/tm-tx39.h
new file mode 100644
index 0000000..ee99a28
--- /dev/null
+++ b/gdb/config/mips/tm-tx39.h
@@ -0,0 +1,39 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define MIPS_EABI 1
+#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
+
+#include "mips/tm-bigmips.h"
+
+#undef  REGISTER_NAMES
+#define REGISTER_NAMES 	\
+    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
+	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
+	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
+	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
+	"sr",	"lo",	"hi",	"bad",	"cause","pc", \
+	"",   	"",   	"",   	"",   	"",   	"",   	"",   	"", \
+	"",   	"",   	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",	"", \
+	"",	"",	"",	"",	"",	"",	"",	"", \
+	"",	"", "config", "cache", "debug", "depc", "epc",	"" \
+    }
diff --git a/gdb/config/mips/tm-tx39l.h b/gdb/config/mips/tm-tx39l.h
new file mode 100644
index 0000000..8ceec72
--- /dev/null
+++ b/gdb/config/mips/tm-tx39l.h
@@ -0,0 +1,39 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define MIPS_EABI 1
+#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
+
+#include "mips/tm-mips.h"
+
+#undef  REGISTER_NAMES
+#define REGISTER_NAMES 	\
+    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
+	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
+	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
+	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
+	"sr",	"lo",	"hi",	"bad",	"cause","pc", \
+	"",   	"",   	"",   	"",   	"",   	"",   	"",   	"", \
+	"",   	"",   	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",  	"",  	"",  	"",  	"",  	"", \
+	"",  	"",  	"",	"", \
+	"",	"",	"",	"",	"",	"",	"",	"", \
+	"",	"", "config", "cache", "debug", "depc", "epc",	"" \
+    }
diff --git a/gdb/config/mips/tm-vr4100.h b/gdb/config/mips/tm-vr4100.h
new file mode 100644
index 0000000..843f49c
--- /dev/null
+++ b/gdb/config/mips/tm-vr4100.h
@@ -0,0 +1,25 @@
+/* Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define MIPS_EABI 1
+#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+#define TARGET_PTR_BIT 64
+
+#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4300.h b/gdb/config/mips/tm-vr4300.h
new file mode 100644
index 0000000..541ca44
--- /dev/null
+++ b/gdb/config/mips/tm-vr4300.h
@@ -0,0 +1,22 @@
+/* Copyright (C) 1993, 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+
+#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4300el.h b/gdb/config/mips/tm-vr4300el.h
new file mode 100644
index 0000000..75e8693
--- /dev/null
+++ b/gdb/config/mips/tm-vr4300el.h
@@ -0,0 +1,22 @@
+/* Copyright (C) 1993, 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+
+#include "mips/tm-mips64.h"
diff --git a/gdb/config/mips/tm-vr5000.h b/gdb/config/mips/tm-vr5000.h
new file mode 100644
index 0000000..b834a77
--- /dev/null
+++ b/gdb/config/mips/tm-vr5000.h
@@ -0,0 +1,23 @@
+/* Copyright (C) 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+#define MIPS_EABI 1
+
+#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr5000el.h b/gdb/config/mips/tm-vr5000el.h
new file mode 100644
index 0000000..c6897d1
--- /dev/null
+++ b/gdb/config/mips/tm-vr5000el.h
@@ -0,0 +1,23 @@
+/* Copyright (C) 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+#define MIPS_EABI 1
+
+#include "mips/tm-mips64.h"
diff --git a/gdb/config/mips/tm-vxmips.h b/gdb/config/mips/tm-vxmips.h
new file mode 100644
index 0000000..392a929
--- /dev/null
+++ b/gdb/config/mips/tm-vxmips.h
@@ -0,0 +1,31 @@
+/* Target machine description for VxWorks MIPS's, for GDB, the GNU debugger.
+   Copyright 1996 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define	GDBINIT_FILENAME	".vxgdbinit"
+
+#define	DEFAULT_PROMPT		"(vxgdb) "
+
+#include "mips/tm-mips.h"
+
+/* FIXME: These are almost certainly wrong. */
+
+/* Number of registers in a ptrace_getregs call. */
+
+#define VX_NUM_REGS (NUM_REGS)
diff --git a/gdb/config/mips/tx39.mt b/gdb/config/mips/tx39.mt
new file mode 100644
index 0000000..8b4c1a9
--- /dev/null
+++ b/gdb/config/mips/tx39.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o dve3900-rom.o monitor.o dsrec.o
+TM_FILE= tm-tx39.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/tx39l.mt b/gdb/config/mips/tx39l.mt
new file mode 100644
index 0000000..3508329
--- /dev/null
+++ b/gdb/config/mips/tx39l.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian mips board, typically an IDT.
+TDEPFILES= mips-tdep.o remote-mips.o dve3900-rom.o monitor.o dsrec.o
+TM_FILE= tm-tx39l.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vr4100.mt b/gdb/config/mips/vr4100.mt
new file mode 100644
index 0000000..c5ae4f9
--- /dev/null
+++ b/gdb/config/mips/vr4100.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr4100.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vr4300.mt b/gdb/config/mips/vr4300.mt
new file mode 100644
index 0000000..22cb25e
--- /dev/null
+++ b/gdb/config/mips/vr4300.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr4300.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vr4300el.mt b/gdb/config/mips/vr4300el.mt
new file mode 100644
index 0000000..cff7241
--- /dev/null
+++ b/gdb/config/mips/vr4300el.mt
@@ -0,0 +1,5 @@
+# Target: Little-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr4300el.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vr5000.mt b/gdb/config/mips/vr5000.mt
new file mode 100644
index 0000000..316c548
--- /dev/null
+++ b/gdb/config/mips/vr5000.mt
@@ -0,0 +1,7 @@
+# Target: Big-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr5000.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
+GDBSERVER_DEPFILES= low-sim.o
+GDBSERVER_LIBS = ../../sim/mips/libsim.a ../../bfd/libbfd.a ../../libiberty/libiberty.a -lm
diff --git a/gdb/config/mips/vr5000el.mt b/gdb/config/mips/vr5000el.mt
new file mode 100644
index 0000000..99687ed
--- /dev/null
+++ b/gdb/config/mips/vr5000el.mt
@@ -0,0 +1,5 @@
+# Target: Little-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr5000el.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vxmips.mt b/gdb/config/mips/vxmips.mt
new file mode 100644
index 0000000..a20cf96
--- /dev/null
+++ b/gdb/config/mips/vxmips.mt
@@ -0,0 +1,3 @@
+# Target: MIPS running VxWorks
+TDEPFILES= mips-tdep.o remote-vx.o remote-vxmips.o xdr_ld.o xdr_ptrace.o xdr_rdb.o
+TM_FILE= tm-vxmips.h
diff --git a/gdb/config/mips/xm-irix3.h b/gdb/config/mips/xm-irix3.h
new file mode 100644
index 0000000..d096594
--- /dev/null
+++ b/gdb/config/mips/xm-irix3.h
@@ -0,0 +1,31 @@
+/* Copyright (C) 1991 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* This is for the iris. */
+
+#define HAVE_TERMIO
+
+#define HOST_BYTE_ORDER BIG_ENDIAN
+
+/* Override register locations in upage for SGI machines */
+#undef REGISTER_U_ADDR
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+  if (regno < PC_REGNUM)				\
+      addr = regno;					\
+  else							\
+      addr = regno + NSIG_HNDLRS; /* Skip over signal handlers */
diff --git a/gdb/config/mips/xm-irix4.h b/gdb/config/mips/xm-irix4.h
new file mode 100644
index 0000000..14d21f0
--- /dev/null
+++ b/gdb/config/mips/xm-irix4.h
@@ -0,0 +1,33 @@
+/* Definitions for irix4 hosting support.
+
+Copyright (C) 1991, 1992 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* This is for the iris. */
+
+#include "mips/xm-irix3.h"
+
+#define BROKEN_SIGINFO_H	/* <sys/siginfo.h> si_pid & si_uid are bogus */
+
+/* Irix 4.0.1 and later have termios.  Not sure about earlier versions.  */
+#undef HAVE_TERMIO
+#define HAVE_TERMIOS
+
+/* This enables reliable signals (and the associated setjmp/longjmp), and gives
+   bsdish prototypes for getpgrp/setpgrg/setgroups and initgroups.  */
+#define _BSD_COMPAT
diff --git a/gdb/config/mips/xm-irix5.h b/gdb/config/mips/xm-irix5.h
new file mode 100644
index 0000000..a64277b
--- /dev/null
+++ b/gdb/config/mips/xm-irix5.h
@@ -0,0 +1,35 @@
+/* Definitions for irix5 hosting support.
+
+Copyright (C) 1993, 1996 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "xm-sysv4.h"
+
+#define HOST_BYTE_ORDER BIG_ENDIAN
+
+/* Override register locations in upage for SGI machines */
+#undef REGISTER_U_ADDR
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+  if (regno < PC_REGNUM)				\
+      addr = regno;					\
+  else							\
+      addr = regno + NSIG_HNDLRS; /* Skip over signal handlers */
+
+/* This enables reliable signals (and the associated setjmp/longjmp), and gives
+   bsdish prototypes for getpgrp/setpgrg/setgroups and initgroups.  */
+#define _BSD_COMPAT
diff --git a/gdb/config/mips/xm-mips.h b/gdb/config/mips/xm-mips.h
new file mode 100644
index 0000000..a2e9a50
--- /dev/null
+++ b/gdb/config/mips/xm-mips.h
@@ -0,0 +1,61 @@
+/* Definitions to make GDB run on a mips box under 4.3bsd.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+   Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin(af@cs.cmu.edu) at CMU
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#if !defined (HOST_BYTE_ORDER)
+#define HOST_BYTE_ORDER LITTLE_ENDIAN
+#endif
+
+#ifdef ultrix
+/* Needed for DECstation core files.  */
+#include <machine/param.h>
+#define KERNEL_U_ADDR UADDR
+
+/* Native Ultrix cc has broken long long support.  */
+#ifndef __GNUC__
+#undef CC_HAS_LONG_LONG
+#endif
+#endif
+
+#if ! defined (__STDC__) && ! defined (offsetof)
+# define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+/* Only used for core files on DECstations.
+   First four registers at u.u_ar0 are saved arguments, and
+   there is no r0 saved.   Float registers are saved
+   in u_pcb.pcb_fpregs, not relative to u.u_ar0.  */
+
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+	{ \
+	  if (regno < FP0_REGNUM) \
+	    addr = blockend + sizeof(int) * (4 + regno - 1); \
+	  else \
+	    addr = offsetof (struct user, u_pcb.pcb_fpregs[0]) + \
+		   sizeof (int) * (regno - FP0_REGNUM); \
+	}
+
+/* Kernel is a bit tenacious about sharing text segments, disallowing bpts.  */
+#define	ONE_PROCESS_WRITETEXT
+
+/* HAVE_SGTTY also works, last we tried.
+
+   But we have termios, at least as of Ultrix 4.2A, so use it.  */
+#define HAVE_TERMIOS
diff --git a/gdb/config/mips/xm-mipsm3.h b/gdb/config/mips/xm-mipsm3.h
new file mode 100644
index 0000000..6a5a73c
--- /dev/null
+++ b/gdb/config/mips/xm-mipsm3.h
@@ -0,0 +1,32 @@
+/* Definitions to make GDB run on a mips box under 4.3bsd.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+   Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin(af@cs.cmu.edu) at CMU
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#if !defined (HOST_BYTE_ORDER)
+#define HOST_BYTE_ORDER LITTLE_ENDIAN
+#endif
+
+#define KERNEL_U_ADDR 0 /* Not needed. */
+
+/* Only used for core files on DECstations. */
+
+#define REGISTER_U_ADDR(addr, blockend, regno) 		\
+	if (regno < 38) addr = (NBPG*UPAGES) + (regno - 38)*sizeof(int);\
+	else addr = 0; /* ..somewhere in the pcb */
diff --git a/gdb/config/mips/xm-mipsv4.h b/gdb/config/mips/xm-mipsv4.h
new file mode 100644
index 0000000..d80ba43
--- /dev/null
+++ b/gdb/config/mips/xm-mipsv4.h
@@ -0,0 +1,23 @@
+/* Definitions for MIPS running SVR4 hosting support.
+
+Copyright (C) 1994 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "xm-sysv4.h"
+
+#define HOST_BYTE_ORDER BIG_ENDIAN
diff --git a/gdb/config/mips/xm-news-mips.h b/gdb/config/mips/xm-news-mips.h
new file mode 100644
index 0000000..06aac1a
--- /dev/null
+++ b/gdb/config/mips/xm-news-mips.h
@@ -0,0 +1,24 @@
+/* Definitions to make GDB run on a mips box under 4.3bsd.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+   Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Alessandro Forin(af@cs.cmu.edu) at CMU
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#if !defined (HOST_BYTE_ORDER)
+#define HOST_BYTE_ORDER BIG_ENDIAN
+#endif
diff --git a/gdb/config/mips/xm-riscos.h b/gdb/config/mips/xm-riscos.h
new file mode 100644
index 0000000..467f32a
--- /dev/null
+++ b/gdb/config/mips/xm-riscos.h
@@ -0,0 +1,28 @@
+/* Copyright (C) 1993 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define HAVE_TERMIO
+
+#if !defined (HOST_BYTE_ORDER)
+#define HOST_BYTE_ORDER BIG_ENDIAN
+#endif
+
+#define USG 1
+
+/* setjmp.h requires uid_t.  */
+#include <sys/types.h>