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| author | Luis Machado <luis.machado@linaro.org> | 2020-06-15 13:52:27 -0300 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2021-03-24 14:52:08 -0300 |
| commit | c1bd443b4d86e12f2a97856270e40df24c7f3df7 (patch) | |
| tree | 9aae2ce3110607d8710532a75ff12c529f1cd78d /gdb/arch | |
| parent | 0424512519142571509c67e83cd9dc2ed51d2dec (diff) | |
| download | fsf-binutils-gdb-c1bd443b4d86e12f2a97856270e40df24c7f3df7.zip fsf-binutils-gdb-c1bd443b4d86e12f2a97856270e40df24c7f3df7.tar.gz fsf-binutils-gdb-c1bd443b4d86e12f2a97856270e40df24c7f3df7.tar.bz2 | |
AArch64: Add target description/feature for MTE registers
This patch adds a target description and feature "mte" for aarch64.
It includes one new register, tag_ctl, that can be used to configure the
tag generation rules and sync/async modes. It is 64-bit in size.
The patch also adjusts the code that creates the target descriptions at
runtime based on CPU feature checks.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Take MTE flag into
account.
Slight refactor to hwcap flag checking.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for
MTE.
(aarch64_read_description): Add mte_p parameter and update to use it.
Update the documentation.
(aarch64_gdbarch_init): Update call to aarch64_read_description.
* aarch64-tdep.h (aarch64_read_description): Add mte_p parameter.
* arch/aarch64.c: Include ../features/aarch64-mte.c.
(aarch64_create_target_description): Add mte_p parameter and update
the code to use it.
* arch/aarch64.h (aarch64_create_target_description): Add mte_p
parameter.
* features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml.
* features/aarch64-mte.c: New file, generated.
* features/aarch64-mte.xml: New file.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to
aarch64_linux_read_description.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag
into account.
* linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension
for MTE.
(aarch64_linux_read_description): Add mte_p parameter and update to
use it.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p
parameter.
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/aarch64.c | 7 | ||||
| -rw-r--r-- | gdb/arch/aarch64.h | 7 |
2 files changed, 11 insertions, 3 deletions
diff --git a/gdb/arch/aarch64.c b/gdb/arch/aarch64.c index d243116..c38f831 100644 --- a/gdb/arch/aarch64.c +++ b/gdb/arch/aarch64.c @@ -23,11 +23,12 @@ #include "../features/aarch64-fpu.c" #include "../features/aarch64-sve.c" #include "../features/aarch64-pauth.c" +#include "../features/aarch64-mte.c" /* See arch/aarch64.h. */ target_desc * -aarch64_create_target_description (uint64_t vq, bool pauth_p) +aarch64_create_target_description (uint64_t vq, bool pauth_p, bool mte_p) { target_desc_up tdesc = allocate_target_description (); @@ -47,5 +48,9 @@ aarch64_create_target_description (uint64_t vq, bool pauth_p) if (pauth_p) regnum = create_feature_aarch64_pauth (tdesc.get (), regnum); + /* Memory tagging extension registers. */ + if (mte_p) + regnum = create_feature_aarch64_mte (tdesc.get (), regnum); + return tdesc.release (); } diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index 6c98d5f..0eb702c 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -25,9 +25,12 @@ /* Create the aarch64 target description. A non zero VQ value indicates both the presence of SVE and the Vector Quotient - the number of 128bit chunks in an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH - feature. */ + feature. -target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p); + MTE_P indicates the presence of the Memory Tagging Extension feature. */ + +target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p, + bool mte_p); /* Register numbers of various important registers. Note that on SVE, the Z registers reuse the V register numbers and the V |