gdb/riscv: rewrite target description validation, add rv32e support

This commit started as adding rv32e support to gdb.  The rv32e
architecture is a cut-down rv32i, it only has 16 x-registers compared
to the usual 32, and an rv32e target should not have any floating
point registers.

In order to add this I needed to adjust the target description
validation checks that are performed from riscv_gdbarch_init, and I
finally got fed up with the current scheme of doing these checks and
rewrote this code.

Unfortunately the rv32e changes are currently mixed in with the
rewrite of the validation scheme.  I could split these apart if anyone
is really interested in seeing these two ideas as separate patches.

The main idea behind this change is that where previously I tried to
have a purely data driven approach, a set of tables one for each
expected feature, and then a single generic function that would
validate a feature given a table, I have created a new class for each
feature.  Each class has its own check member function which allows
the logic for how to check each feature to be different.  I think the
new scheme is much easier to follow.

There are some other changes that I made to the validation code as
part of this commit.

I've relaxed some of the checks related to the floating point CSRs.
Previously the 3 CSRs fflags, frm, and fcsr all had to be present in
either the fpu feature or the csr feature.  This requirement is now
relaxed, if the CSRs are not present then gdb will not reject the
target description.  My thinking here is that there's no gdb
functionality that specifically requires these registers, and so, if a
target offers a description without these registers nothing else in
gdb should stop working.

And as part of the rv32e support targets now only have to provide the
first 16 x-registers and $pc.  The second half of the x-registers (x16
-> x31) are now optional.

gdb/ChangeLog:

	* arch/riscv.c: Include 'rv32e-xregs.c'.
	(riscv_create_target_description): Update to handle rv32e.
	* arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New
	member variable.
	<operator==>: Update to account for new field.
	<hash>: Likewise.
	* features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml.
	* features/riscv/rv32e-xregs.c: Generated.
	* features/riscv/rv32e-xregs.xml: New file.
	* riscv-tdep.c (riscv_debug_breakpoints): Move from later in the
	file.
	(riscv_debug_infcall): Likewise.
	(riscv_debug_unwinder): Likewise.
	(riscv_debug_gdbarch): Likewise.
	(enum riscv_register_required_status): Delete.
	(struct riscv_register_feature): Add constructor, delete default
	constructor, copy, and assign constructors.
	(struct riscv_register_feature::register_info) <required>: Delete.
	<check>: Update comment and arguments.
	(struct riscv_register_feature) <name>: Change to member function.
	<prefer_first_name>: Delete.
	<tdesc_feature>: New member function.
	<registers>: Rename to...
	<m_registers>: ...this.
	<m_feature_name>: New member variable.
	(riscv_register_feature::register_info::check): Update arguments.
	(riscv_xreg_feature): Rewrite as class, create a single static
	instance of the class.
	(riscv_freg_feature): Likewise.
	(riscv_virtual_feature): Likewise.
	(riscv_csr_feature): Likewise.
	(riscv_create_csr_aliases): Has become a member function inside
	riscv_csr_feature class.
	(riscv_abi_embedded): New function definition.
	(riscv_register_name): Adjust to use new feature objects.
	(struct riscv_call_info) <riscv_call_info>: Check for rv32e abi,
	and adjust available argument registers.
	(riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag.
	(riscv_check_tdesc_feature): Delete.
	(riscv_tdesc_unknown_reg): Adjust to use new feature objects.
	(riscv_gdbarch_init): Delete target description checking code, and
	instead call to the new feature objects to perform the checks.
	Reorder handling of no abi information case, allows small code
	simplification.
	(_initialize_riscv_tdep): Remove call, this is now done in the
	riscv_csr_feature constructor.
	* riscv-tdep.h (riscv_abi_embedded): Declare.

2 files changed, 20 insertions, 4 deletions

diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
index a6538de..64f3940 100644
--- a/gdb/arch/riscv.c
+++ b/gdb/arch/riscv.c
@@ -24,6 +24,7 @@
 #include "../features/riscv/64bit-cpu.c"
 #include "../features/riscv/32bit-fpu.c"
 #include "../features/riscv/64bit-fpu.c"
+#include "../features/riscv/rv32e-xregs.c"
 
 #ifndef GDBSERVER
 #define STATIC_IN_GDB static
@@ -43,7 +44,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
   std::string arch_name = "riscv";
 
   if (features.xlen == 4)
-    arch_name.append (":rv32i");
+    {
+      if (features.embedded)
+	arch_name.append (":rv32e");
+      else
+	arch_name.append (":rv32i");
+    }
   else if (features.xlen == 8)
     arch_name.append (":rv64i");
   else if (features.xlen == 16)
@@ -63,7 +69,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
 
   /* For now we only support creating 32-bit or 64-bit x-registers.  */
   if (features.xlen == 4)
-    regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
+    {
+      if (features.embedded)
+	regnum = create_feature_riscv_rv32e_xregs (tdesc.get (), regnum);
+      else
+	regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
+    }
   else if (features.xlen == 8)
     regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
 
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 26db0da..f91c077 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -46,10 +46,13 @@ struct riscv_gdbarch_features
      that there are no f-registers.  No other value is valid.  */
   int flen = 0;
 
+  /* When true this target is RV32E.  */
+  bool embedded = false;
+
   /* Equality operator.  */
   bool operator== (const struct riscv_gdbarch_features &rhs) const
   {
-    return (xlen == rhs.xlen && flen == rhs.flen);
+    return (xlen == rhs.xlen && flen == rhs.flen && embedded == rhs.embedded);
   }
 
   /* Inequality operator.  */
@@ -61,7 +64,9 @@ struct riscv_gdbarch_features
   /* Used by std::unordered_map to hash feature sets.  */
   std::size_t hash () const noexcept
   {
-    std::size_t val = ((xlen & 0x1f) << 5 | (flen & 0x1f) << 0);
+    std::size_t val = ((embedded ? 1 : 0) << 10
+		       | (xlen & 0x1f) << 5
+		       | (flen & 0x1f) << 0);
     return val;
   }
 };