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author | Jim Wilson <jimw@sifive.com> | 2020-02-19 14:51:07 -0800 |
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committer | Jim Wilson <jimw@sifive.com> | 2020-02-19 14:51:07 -0800 |
commit | fa16423949fc78b3d9c499eddefa91b99228fbc9 (patch) | |
tree | a7092b040556f52f3d0e236b1786524a0f32bb07 /gas | |
parent | 741cb83912fffbc65784168204ce1a597e0fbd26 (diff) | |
download | fsf-binutils-gdb-fa16423949fc78b3d9c499eddefa91b99228fbc9.zip fsf-binutils-gdb-fa16423949fc78b3d9c499eddefa91b99228fbc9.tar.gz fsf-binutils-gdb-fa16423949fc78b3d9c499eddefa91b99228fbc9.tar.bz2 |
RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
gas/
* testsuite/gas/riscv/c-add-addi.d: New testcase.
* testsuite/gas/riscv/c-add-addi.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
c.mv/c.li if rs1 is zero.
Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/c-add-addi.d | 11 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/c-add-addi.s | 3 |
3 files changed, 19 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index e722633..92869a3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-02-19 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/c-add-addi.d: New testcase. + * testsuite/gas/riscv/c-add-addi.s: Likewise. + 2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com> PR 25576 diff --git a/gas/testsuite/gas/riscv/c-add-addi.d b/gas/testsuite/gas/riscv/c-add-addi.d new file mode 100644 index 0000000..14913df --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+4605[ ]+li[ ]+a2,1 +[ ]+2:[ ]+852e[ ]+mv[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/c-add-addi.s b/gas/testsuite/gas/riscv/c-add-addi.s new file mode 100644 index 0000000..5274491 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.s @@ -0,0 +1,3 @@ +.option rvc +addi a2, zero, 1 +add a0, zero, a1 |