Power10 Reduced precision outer product operations

include/
	* opcode/ppc.h (PPC_OPERAND_ACC): Define.  Renumber following
	PPC_OPERAND defines.
opcodes/
	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
	(md_assemble): Check acc specified in correct operand.
	* testsuite/gas/ppc/outerprod.d,
	* testsuite/gas/ppc/outerprod.s,
	* testsuite/gas/ppc/vsx4.d,
	* testsuite/gas/ppc/vsx4.s: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.

7 files changed, 207 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3a81d84..0fe429a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,4 +1,15 @@
 2020-05-11  Alan Modra  <amodra@gmail.com>
+	    Peter Bergner  <bergner@linux.ibm.com>
+
+	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
+	(md_assemble): Check acc specified in correct operand.
+	* testsuite/gas/ppc/outerprod.d,
+	* testsuite/gas/ppc/outerprod.s,
+	* testsuite/gas/ppc/vsx4.d,
+	* testsuite/gas/ppc/vsx4.s: New tests.
+	* testsuite/gas/ppc/ppc.exp: Run them.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
 
 	* testsuite/gas/ppc/simd_perm.d,
 	* testsuite/gas/ppc/simd_perm.s: New test.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index e0da3bf..4a07f0b 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -346,6 +346,16 @@ struct pd_reg
 
 static const struct pd_reg pre_defined_registers[] =
 {
+  /* VSX accumulators.  */
+  { "a0", 0, PPC_OPERAND_ACC },
+  { "a1", 1, PPC_OPERAND_ACC },
+  { "a2", 2, PPC_OPERAND_ACC },
+  { "a3", 3, PPC_OPERAND_ACC },
+  { "a4", 4, PPC_OPERAND_ACC },
+  { "a5", 5, PPC_OPERAND_ACC },
+  { "a6", 6, PPC_OPERAND_ACC },
+  { "a7", 7, PPC_OPERAND_ACC },
+
   /* Condition Registers */
   { "cr.0", 0, PPC_OPERAND_CR_REG },
   { "cr.1", 1, PPC_OPERAND_CR_REG },
@@ -3569,7 +3579,7 @@ md_assemble (char *str)
 	       & ~operand->flags
 	       & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR
 		  | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG
-		  | PPC_OPERAND_SPR | PPC_OPERAND_GQR)) != 0
+		  | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0
 	      && !((ex.X_md & PPC_OPERAND_GPR) != 0
 		   && ex.X_add_number != 0
 		   && (operand->flags & PPC_OPERAND_GPR_0) != 0))
diff --git a/gas/testsuite/gas/ppc/outerprod.d b/gas/testsuite/gas/ppc/outerprod.d
new file mode 100644
index 0000000..613fb18
--- /dev/null
+++ b/gas/testsuite/gas/ppc/outerprod.d
@@ -0,0 +1,104 @@
+#as: -mpower10
+#objdump: -dr -Mpower10
+#name: outer product reduced precision
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*:	(7e 80 01 62|62 01 80 7e) 	xxmfacc a5
+.*:	(7f 01 01 62|62 01 01 7f) 	xxmtacc a6
+.*:	(7f 83 01 62|62 01 83 7f) 	xxsetaccz a7
+.*:	(ec 1f f1 1e|1e f1 1f ec) 	xvi4ger8 a0,vs63,vs62
+.*:	(ec 9d e1 16|16 e1 9d ec) 	xvi4ger8pp a1,vs61,vs60
+.*:	(07 90 ff fe|fe ff 90 07) 	pmxvi4ger8 a2,vs59,vs58,15,14,255
+.*:	(ed 1b d1 1e|1e d1 1b ed) 
+.*:	(07 90 80 78|78 80 90 07) 	pmxvi4ger8pp a3,vs57,vs56,7,8,128
+.*:	(ed 99 c1 16|16 c1 99 ed) 
+.*:	(ee 17 b0 1e|1e b0 17 ee) 	xvi8ger4 a4,vs55,vs54
+.*:	(ee 95 a0 16|16 a0 95 ee) 	xvi8ger4pp a5,vs53,vs52
+.*:	(07 90 b0 dc|dc b0 90 07) 	pmxvi8ger4 a6,vs51,vs50,13,12,11
+.*:	(ef 13 90 1e|1e 90 13 ef) 
+.*:	(07 90 80 a9|a9 80 90 07) 	pmxvi8ger4pp a7,vs49,vs48,10,9,8
+.*:	(ef 91 80 16|16 80 91 ef) 
+.*:	(ec 0f 71 5e|5e 71 0f ec) 	xvi16ger2s a0,vs47,vs46
+.*:	(ec 8d 61 56|56 61 8d ec) 	xvi16ger2spp a1,vs45,vs44
+.*:	(07 90 c0 76|76 c0 90 07) 	pmxvi16ger2s a2,vs43,vs42,7,6,3
+.*:	(ed 0b 51 5e|5e 51 0b ed) 
+.*:	(07 90 80 54|54 80 90 07) 	pmxvi16ger2spp a3,vs41,vs40,5,4,2
+.*:	(ed 89 41 56|56 41 89 ed) 
+.*:	(ee 07 30 9e|9e 30 07 ee) 	xvf16ger2 a4,vs39,vs38
+.*:	(ee 85 20 96|96 20 85 ee) 	xvf16ger2pp a5,vs37,vs36
+.*:	(ef 03 14 96|96 14 03 ef) 	xvf16ger2pn a6,vs35,vs34
+.*:	(ef 81 02 96|96 02 81 ef) 	xvf16ger2np a7,vs33,vs32
+.*:	(ec 04 2e 90|90 2e 04 ec) 	xvf16ger2nn a0,vs4,vs5
+.*:	(07 90 40 32|32 40 90 07) 	pmxvf16ger2 a1,vs2,vs3,3,2,1
+.*:	(ec 82 18 98|98 18 82 ec) 
+.*:	(07 90 00 10|10 00 90 07) 	pmxvf16ger2pp a2,vs4,vs5,1,0,0
+.*:	(ed 04 28 90|90 28 04 ed) 
+.*:	(07 90 c0 fe|fe c0 90 07) 	pmxvf16ger2pn a3,vs6,vs7,15,14,3
+.*:	(ed 86 3c 90|90 3c 86 ed) 
+.*:	(07 90 80 dc|dc 80 90 07) 	pmxvf16ger2np a4,vs8,vs9,13,12,2
+.*:	(ee 08 4a 90|90 4a 08 ee) 
+.*:	(07 90 40 ba|ba 40 90 07) 	pmxvf16ger2nn a5,vs10,vs11,11,10,1
+.*:	(ee 8a 5e 90|90 5e 8a ee) 
+.*:	(ef 0c 68 d8|d8 68 0c ef) 	xvf32ger a6,vs12,vs13
+.*:	(ef 8e 78 d0|d0 78 8e ef) 	xvf32gerpp a7,vs14,vs15
+.*:	(ec 10 8c d0|d0 8c 10 ec) 	xvf32gerpn a0,vs16,vs17
+.*:	(ec 92 9a d0|d0 9a 92 ec) 	xvf32gernp a1,vs18,vs19
+.*:	(ed 14 ae d0|d0 ae 14 ed) 	xvf32gernn a2,vs20,vs21
+.*:	(07 90 00 98|98 00 90 07) 	pmxvf32ger a3,vs22,vs23,9,8
+.*:	(ed 96 b8 d8|d8 b8 96 ed) 
+.*:	(07 90 00 76|76 00 90 07) 	pmxvf32gerpp a4,vs24,vs25,7,6
+.*:	(ee 18 c8 d0|d0 c8 18 ee) 
+.*:	(07 90 00 54|54 00 90 07) 	pmxvf32gerpn a5,vs26,vs27,5,4
+.*:	(ee 9a dc d0|d0 dc 9a ee) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(07 90 00 32|32 00 90 07) 	pmxvf32gernp a6,vs28,vs29,3,2
+.*:	(ef 1c ea d0|d0 ea 1c ef) 
+.*:	(07 90 00 10|10 00 90 07) 	pmxvf32gernn a7,vs0,vs1,1,0
+.*:	(ef 80 0e d0|d0 0e 80 ef) 
+.*:	(ec 04 29 d8|d8 29 04 ec) 	xvf64ger a0,vs4,vs5
+.*:	(ec 88 49 d0|d0 49 88 ec) 	xvf64gerpp a1,vs8,vs9
+.*:	(ed 02 15 d0|d0 15 02 ed) 	xvf64gerpn a2,vs2,vs2
+.*:	(ed 84 1b d0|d0 1b 84 ed) 	xvf64gernp a3,vs4,vs3
+.*:	(ee 04 27 d0|d0 27 04 ee) 	xvf64gernn a4,vs4,vs4
+.*:	(07 90 00 f0|f0 00 90 07) 	pmxvf64ger a5,vs6,vs5,15,0
+.*:	(ee 86 29 d8|d8 29 86 ee) 
+.*:	(07 90 00 e4|e4 00 90 07) 	pmxvf64gerpp a6,vs6,vs6,14,1
+.*:	(ef 06 31 d0|d0 31 06 ef) 
+.*:	(07 90 00 d8|d8 00 90 07) 	pmxvf64gerpn a7,vs8,vs7,13,2
+.*:	(ef 88 3d d0|d0 3d 88 ef) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(07 90 00 cc|cc 00 90 07) 	pmxvf64gernp a0,vs4,vs5,12,3
+.*:	(ec 04 2b d0|d0 2b 04 ec) 
+.*:	(07 90 00 a0|a0 00 90 07) 	pmxvf64gernn a1,vs2,vs1,10,0
+.*:	(ec 82 0f d0|d0 0f 82 ec) 
+.*:	(ed 03 21 90|90 21 03 ed) 	xvbf16ger2pp a2,vs3,vs4
+.*:	(ed 84 29 98|98 29 84 ed) 	xvbf16ger2 a3,vs4,vs5
+.*:	(ee 05 33 90|90 33 05 ee) 	xvbf16ger2np a4,vs5,vs6
+.*:	(ee 86 3d 90|90 3d 86 ee) 	xvbf16ger2pn a5,vs6,vs7
+.*:	(ef 07 47 90|90 47 07 ef) 	xvbf16ger2nn a6,vs7,vs8
+.*:	(07 90 c0 ff|ff c0 90 07) 	pmxvbf16ger2pp a7,vs8,vs9,15,15,3
+.*:	(ef 88 49 90|90 49 88 ef) 
+.*:	(07 90 80 cc|cc 80 90 07) 	pmxvbf16ger2 a0,vs9,vs10,12,12,2
+.*:	(ec 09 51 98|98 51 09 ec) 
+.*:	(07 90 40 aa|aa 40 90 07) 	pmxvbf16ger2np a1,vs10,vs11,10,10,1
+.*:	(ec 8a 5b 90|90 5b 8a ec) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(07 90 00 dd|dd 00 90 07) 	pmxvbf16ger2pn a2,vs12,vs13,13,13,0
+.*:	(ed 0c 6d 90|90 6d 0c ed) 
+.*:	(07 90 c0 ee|ee c0 90 07) 	pmxvbf16ger2nn a3,vs16,vs17,14,14,3
+.*:	(ed 90 8f 90|90 8f 90 ed) 
+.*:	(ee 00 0b 1e|1e 0b 00 ee) 	xvi8ger4spp a4,vs32,vs33
+.*:	(07 90 f0 ff|ff f0 90 07) 	pmxvi8ger4spp a5,vs34,vs35,15,15,15
+.*:	(ee 82 1b 1e|1e 1b 82 ee) 
+.*:	(ef 04 2a 5e|5e 2a 04 ef) 	xvi16ger2 a6,vs36,vs37
+.*:	(ef 86 3b 5e|5e 3b 86 ef) 	xvi16ger2pp a7,vs38,vs39
+.*:	(07 90 40 ff|ff 40 90 07) 	pmxvi16ger2 a0,vs38,vs39,15,15,1
+.*:	(ec 06 3a 5e|5e 3a 06 ec) 
+.*:	(07 90 80 cc|cc 80 90 07) 	pmxvi16ger2pp a1,vs40,vs41,12,12,2
+.*:	(ec 88 4b 5e|5e 4b 88 ec) 
+#pass
diff --git a/gas/testsuite/gas/ppc/outerprod.s b/gas/testsuite/gas/ppc/outerprod.s
new file mode 100644
index 0000000..1f02c15
--- /dev/null
+++ b/gas/testsuite/gas/ppc/outerprod.s
@@ -0,0 +1,63 @@
+	.text
+_start:
+	xxmfacc	5
+	xxmtacc 6
+	xxsetaccz 7
+	xvi4ger8 0,63,62
+	xvi4ger8pp 1,61,60
+	pmxvi4ger8 2,59,58,15,14,255
+	pmxvi4ger8pp 3,57,56,7,8,128
+	xvi8ger4 4,55,54
+	xvi8ger4pp 5,53,52
+	pmxvi8ger4 6,51,50,13,12,11
+	pmxvi8ger4pp 7,49,48,10,9,8
+	xvi16ger2s 0,47,46
+	xvi16ger2spp 1,45,44
+	pmxvi16ger2s 2,43,42,7,6,3
+	pmxvi16ger2spp 3,41,40,5,4,2
+	xvf16ger2 4,39,38
+	xvf16ger2pp 5,37,36
+	xvf16ger2pn 6,35,34
+	xvf16ger2np 7,33,32
+	xvf16ger2nn 0,4,5
+	pmxvf16ger2 1,2,3,3,2,1
+	pmxvf16ger2pp 2,4,5,1,0,0
+	pmxvf16ger2pn 3,6,7,15,14,3
+	pmxvf16ger2np 4,8,9,13,12,2
+	pmxvf16ger2nn 5,10,11,11,10,1
+	xvf32ger 6,12,13
+	xvf32gerpp 7,14,15
+	xvf32gerpn 0,16,17
+	xvf32gernp 1,18,19
+	xvf32gernn 2,20,21
+	pmxvf32ger 3,22,23,9,8
+	pmxvf32gerpp 4,24,25,7,6
+	pmxvf32gerpn 5,26,27,5,4
+	pmxvf32gernp 6,28,29,3,2
+	pmxvf32gernn 7,0,1,1,0
+	xvf64ger 0,4,5
+	xvf64gerpp 1,8,9
+	xvf64gerpn 2,2,2
+	xvf64gernp 3,4,3
+	xvf64gernn 4,4,4
+	pmxvf64ger 5,6,5,15,0
+	pmxvf64gerpp 6,6,6,14,1
+	pmxvf64gerpn 7,8,7,13,2
+	pmxvf64gernp 0,4,5,12,3
+	pmxvf64gernn 1,2,1,10,0
+	xvbf16ger2pp 2,3,4
+	xvbf16ger2 3,4,5
+	xvbf16ger2np 4,5,6
+	xvbf16ger2pn 5,6,7
+	xvbf16ger2nn 6,7,8
+	pmxvbf16ger2pp 7,8,9,15,15,3
+	pmxvbf16ger2 0,9,10,12,12,2
+	pmxvbf16ger2np 1,10,11,10,10,1
+	pmxvbf16ger2pn 2,12,13,13,13,0
+	pmxvbf16ger2nn 3,16,17,14,14,3
+	xvi8ger4spp 4,32,33
+	pmxvi8ger4spp 5,34,35,15,15,15
+	xvi16ger2 6,36,37
+	xvi16ger2pp 7,38,39
+	pmxvi16ger2 0,38,39,15,15,1
+	pmxvi16ger2pp 1,40,41,12,12,2
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index afa53f3..34cc82c9 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -124,6 +124,7 @@ run_dump_test "power10"
 run_dump_test "vsx"
 run_dump_test "vsx2"
 run_dump_test "vsx3"
+run_dump_test "vsx4"
 run_dump_test "htm"
 run_dump_test "titan"
 run_dump_test "prefix-align"
@@ -136,3 +137,4 @@ run_dump_test "vec_mul"
 run_dump_test "vsx_32byte"
 run_dump_test "int128"
 run_dump_test "simd_perm"
+run_dump_test "outerprod"
diff --git a/gas/testsuite/gas/ppc/vsx4.d b/gas/testsuite/gas/ppc/vsx4.d
new file mode 100644
index 0000000..657a8ae
--- /dev/null
+++ b/gas/testsuite/gas/ppc/vsx4.d
@@ -0,0 +1,12 @@
+#as: -mpower10
+#objdump: -dr -Mpower10
+#name: VSX ISA power10 instructions
+
+.*
+
+Disassembly of section \.text:
+
+0+0 <vsx4>:
+.*:	(f0 50 6f 6f|6f 6f 50 f0) 	xvcvbf16sp vs34,vs45
+.*:	(f1 f1 27 6f|6f 27 f1 f1) 	xvcvspbf16 vs47,vs36
+#pass
diff --git a/gas/testsuite/gas/ppc/vsx4.s b/gas/testsuite/gas/ppc/vsx4.s
new file mode 100644
index 0000000..290f595
--- /dev/null
+++ b/gas/testsuite/gas/ppc/vsx4.s
@@ -0,0 +1,4 @@
+	.text
+vsx4:
+	xvcvbf16sp	34,45
+	xvcvspbf16	47,36