diff options
author | Vineet Gupta <vineetg@rivosinc.com> | 2021-12-20 18:34:13 -0800 |
---|---|---|
committer | Nelson Chu <nelson.chu@sifive.com> | 2021-12-24 15:17:52 +0800 |
commit | a63375ac337903d4394b2d88788353d06cf7a086 (patch) | |
tree | 30b22f80ca8d3441085115169e27be536f8d63d7 /gas | |
parent | 5c3ffbc4dd9454c56598e28a25d8d0c0faf1e8bc (diff) | |
download | fsf-binutils-gdb-a63375ac337903d4394b2d88788353d06cf7a086.zip fsf-binutils-gdb-a63375ac337903d4394b2d88788353d06cf7a086.tar.gz fsf-binutils-gdb-a63375ac337903d4394b2d88788353d06cf7a086.tar.bz2 |
RISC-V: Hypervisor ext: support Privileged Spec 1.12
This is the Hypervisor Extension 1.0
- Hypervisor Memory-Management Instructions
HFENCE.VVMA, HFENCE.GVMA,
- Hypervisor Virtual Machine Load and Store Instructions
HLV.B, HLV.BU, HSV.B,
HLV.H, HLV.HU, HLVX.HU, HSB.H,
HLV.W, HLV.WU, HLVX.WU, HSV.W,
HLV.D, HSV.D
- Hypervisor CSRs (some new, some address changed)
hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,
Note that following were added already as part of svinval extension
support:
HINVAL.GVMA, HINVAL.VVMA
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
bfd/
* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
* config/tc-riscv.c (abort_version): Updated comment.
(validate_riscv_insn): Annotate switch-break.
* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
* testsuite/gas/riscv/h-ext-32.s: Likewise.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
instrcutions.
opcodes/
* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/config/tc-riscv.c | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/h-ext-32.d | 82 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/h-ext-32.s | 73 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/h-ext-64.d | 81 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/h-ext-64.s | 72 |
5 files changed, 313 insertions, 5 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e806121..dbf0e23 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -82,7 +82,7 @@ struct riscv_csr_extra enum riscv_spec_class define_version; /* Record the CSR is aborted/invalid from which versions. If it isn't - aborted in the current version, then it should be CSR_CLASS_VDRAFT. */ + aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */ enum riscv_spec_class abort_version; /* The CSR may have more than one setting. */ @@ -1104,7 +1104,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) default: goto unknown_validate_operand; } - break; + break; /* end RVC */ case 'V': /* RVV */ switch (*++oparg) { @@ -1128,7 +1128,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) default: goto unknown_validate_operand; } - break; + break; /* end RVV */ case ',': break; case '(': break; case ')': break; @@ -2605,7 +2605,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, default: goto unknown_riscv_ip_operand; } - break; + break; /* end RVC */ case 'V': /* RVV */ switch (*++oparg) @@ -2771,7 +2771,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, default: goto unknown_riscv_ip_operand; } - break; + break; /* end RVV */ case ',': ++argnum; diff --git a/gas/testsuite/gas/riscv/h-ext-32.d b/gas/testsuite/gas/riscv/h-ext-32.d new file mode 100644 index 0000000..870b847 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.d @@ -0,0 +1,82 @@ +#as: -march=rv32i -mpriv-spec=1.12 +#source: h-ext-32.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+22000073[ ]+hfence.vvma +[ ]+[0-9a-f]+:[ ]+22050073[ ]+hfence.vvma[ ]+a0 +[ ]+[0-9a-f]+:[ ]+22b00073[ ]+hfence.vvma[ ]+zero,a1 +[ ]+[0-9a-f]+:[ ]+22c58073[ ]+hfence.vvma[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+62000073[ ]+hfence.gvma +[ ]+[0-9a-f]+:[ ]+62050073[ ]+hfence.gvma[ ]+a0 +[ ]+[0-9a-f]+:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1 +[ ]+[0-9a-f]+:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+61a02573[ ]+csrr[ ]+a0,henvcfgh +[ ]+[0-9a-f]+:[ ]+61a59073[ ]+csrw[ ]+henvcfgh,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah +[ ]+[0-9a-f]+:[ ]+61559073[ ]+csrw[ ]+htimedeltah,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-32.s b/gas/testsuite/gas/riscv/h-ext-32.s new file mode 100644 index 0000000..63b0c9a --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.s @@ -0,0 +1,73 @@ + hfence.vvma + hfence.vvma a0 + hfence.vvma x0, a1 + hfence.vvma a1, a2 + hfence.gvma + hfence.gvma a0 + hfence.gvma x0, a1 + hfence.gvma a1, a2 + + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlvx.wu a2, (a3) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, henvcfgh + csrw henvcfgh, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, htimedeltah + csrw htimedeltah, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.d b/gas/testsuite/gas/riscv/h-ext-64.d new file mode 100644 index 0000000..f948c4d --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.d @@ -0,0 +1,81 @@ +#as: -march=rv64i -mpriv-spec=1.12 +#source: h-ext-64.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+22000073[ ]+hfence.vvma +[ ]+[0-9a-f]+:[ ]+22050073[ ]+hfence.vvma[ ]+a0 +[ ]+[0-9a-f]+:[ ]+22b00073[ ]+hfence.vvma[ ]+zero,a1 +[ ]+[0-9a-f]+:[ ]+22c58073[ ]+hfence.vvma[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+62000073[ ]+hfence.gvma +[ ]+[0-9a-f]+:[ ]+62050073[ ]+hfence.gvma[ ]+a0 +[ ]+[0-9a-f]+:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1 +[ ]+[0-9a-f]+:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6816c673[ ]+hlv.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6c0746f3[ ]+hlv.d[ ]+a3,\(a4\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6ea5c073[ ]+hsv.d[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.s b/gas/testsuite/gas/riscv/h-ext-64.s new file mode 100644 index 0000000..3f7a5b7 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.s @@ -0,0 +1,72 @@ + hfence.vvma + hfence.vvma a0 + hfence.vvma x0, a1 + hfence.vvma a1, a2 + hfence.gvma + hfence.gvma a0 + hfence.gvma x0, a1 + hfence.gvma a1, a2 + + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlv.wu a2, (a3) + hlvx.wu a2, (a3) + hlv.d a3, (a4) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + hsv.d a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 |