[ gas/ChangeLog ]

	* config/tc-mips.c (macro_build): Test for currently active
	mips16 option.
	(mips16_ip): Reject invalid opcodes.

	[ opcodes/ChangeLog ]
	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.

9 files changed, 190 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d8ea270..39dfcc4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Test for currently active
+	mips16 option.
+	(mips16_ip): Reject invalid opcodes.
+
 2006-05-11  Carlos O'Donell  <carlos@codesourcery.com>
 
 	* doc/as.texinfo: Rename "Index" to "AS Index",
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 3108d0a..75c3ae9 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -3015,7 +3015,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	 || mo->pinfo == INSN_MACRO
 	 || !OPCODE_IS_MEMBER (mo,
 			       (mips_opts.isa
-				| (file_ase_mips16 ? INSN_MIPS16 : 0)
+				| (mips_opts.mips16 ? INSN_MIPS16 : 0)
 				| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			       mips_opts.arch)
 	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
@@ -8032,6 +8032,9 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+			     /* We don't check for mips_opts.mips16 here since
+			        we want to allow jalx if -mips16 was specified
+			        on the command line.  */
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
@@ -9467,8 +9470,38 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   argsstart = s;
   for (;;)
     {
+      bfd_boolean ok;
+
       assert (strcmp (insn->name, str) == 0);
 
+      if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
+	ok = TRUE;
+      else
+	ok = FALSE;
+
+      if (! ok)
+	{
+	  if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
+	      && strcmp (insn->name, insn[1].name) == 0)
+	    {
+	      ++insn;
+	      continue;
+	    }
+	  else
+	    {
+	      if (!insn_error)
+		{
+		  static char buf[100];
+		  sprintf (buf,
+			   _("opcode not supported on this processor: %s (%s)"),
+			   mips_cpu_info_from_arch (mips_opts.arch)->name,
+			   mips_cpu_info_from_isa (mips_opts.isa)->name);
+		  insn_error = buf;
+		}
+	      return;
+	    }
+	}
+
       create_insn (ip, insn);
       imm_expr.X_op = O_absent;
       imm_reloc[0] = BFD_RELOC_UNUSED;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e9745b1..2332821 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips.exp: Run new tests.
+	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
+	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
+
 2006-05-11  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/local_function.d: New test.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a65a4c5..e275107 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -777,8 +777,12 @@ if { [istarget mips*-*-vxworks*] } {
 	}
     }
     if { !$no_mips16 } { 
+        # Check MIPS16e extensions
+        run_dump_test_arches "mips16e" 	[mips_arch_list_matching mips32]
         run_dump_test "mips16e-jrc"
         run_dump_test "mips16e-save"
+        run_dump_test "mips16e-64"
+        run_list_test "mips16e-64" "-march=mips32"
     }
     run_dump_test "vxworks1"
     run_dump_test "vxworks1-xgot"
diff --git a/gas/testsuite/gas/mips/mips16e-64.d b/gas/testsuite/gas/mips/mips16e-64.d
new file mode 100644
index 0000000..9eb098f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -mmips:16
+#as: -march=mips64
+#name: MIPS16e-64
+#source: mips16e-64.s
+
+# Test the 64bit instructions of mips16e.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+0x00000000 ecd1      	sew	\$4
+0x00000002 ec51      	zew	\$4
+0x00000004 6500      	nop
+0x00000006 6500      	nop
+0x00000008 6500      	nop
+0x0000000a 6500      	nop
+0x0000000c 6500      	nop
+0x0000000e 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e-64.l b/gas/testsuite/gas/mips/mips16e-64.l
new file mode 100644
index 0000000..8df0c05
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: opcode not supported on this processor: .* (.*) `sew'
+.*: Error: opcode not supported on this processor: .* (.*) `zew'
diff --git a/gas/testsuite/gas/mips/mips16e-64.s b/gas/testsuite/gas/mips/mips16e-64.s
new file mode 100644
index 0000000..39b3597
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.s
@@ -0,0 +1,9 @@
+# Test the 64bit instructions of mips16e.
+
+	.text
+	.set	mips16
+
+	sew	$4
+	zew	$4
+
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/mips16e.d b/gas/testsuite/gas/mips/mips16e.d
new file mode 100644
index 0000000..53aa0d3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.d
@@ -0,0 +1,50 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS16e
+#as: -32
+
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> eac0      	jalrc	\$2
+0+0002 <[^>]*> eac0      	jalrc	\$2
+0+0004 <[^>]*> e8a0      	jrc	\$31
+0+0006 <[^>]*> ea80      	jrc	\$2
+0+0008 <[^>]*> eac0      	jalrc	\$2
+0+000a <[^>]*> eac0      	jalrc	\$2
+0+000c <[^>]*> eac0      	jalrc	\$2
+0+000e <[^>]*> eac0      	jalrc	\$2
+0+0010 <[^>]*> e8a0      	jrc	\$31
+0+0012 <[^>]*> ea80      	jrc	\$2
+0+0014 <[^>]*> e8a0      	jrc	\$31
+0+0016 <[^>]*> ea80      	jrc	\$2
+0+0018 <[^>]*> eac0      	jalrc	\$2
+0+001a <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			1a: R_MIPS16_26	foo
+0+001e <[^>]*> 4281      	addiu	\$4,\$2,1
+0+0020 <[^>]*> eac0      	jalrc	\$2
+0+0022 <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			22: R_MIPS16_26	foo
+0+0026 <[^>]*> 6500      	nop
+0+0028 <[^>]*> 6782      	move	\$4,\$2
+0+002a <[^>]*> eac0      	jalrc	\$2
+0+002c <[^>]*> 6782      	move	\$4,\$2
+0+002e <[^>]*> ea80      	jrc	\$2
+0+0030 <[^>]*> 6782      	move	\$4,\$2
+0+0032 <[^>]*> e8a0      	jrc	\$31
+0+0034 <[^>]*> ec91      	seb	\$4
+0+0036 <[^>]*> ecb1      	seh	\$4
+0+0038 <[^>]*> ec11      	zeb	\$4
+0+003a <[^>]*> ec31      	zeh	\$4
+0+003c <[^>]*> 64c1      	save	8,\$31
+0+003e <[^>]*> 64c0      	save	128,\$31
+0+0040 <[^>]*> 64e2      	save	16,\$31,\$16
+0+0042 <[^>]*> 64f2      	save	16,\$31,\$16-\$17
+0+0044 <[^>]*> 64df      	save	120,\$31,\$17
+0+0046 <[^>]*> f010 64e1 	save	136,\$31,\$16
+0+004a <[^>]*> f004 64f2 	save	\$4,16,\$31,\$16-\$17
+0+004e <[^>]*> f308 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20
+0+0052 <[^>]*> f30c 64f2 	save	\$4-\$6,16,\$31,\$16-\$20
+0+0056 <[^>]*> f70e 64d2 	save	\$4-\$7,16,\$31,\$17-\$30
+0+005a <[^>]*> f30a 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20,\$6-\$7
+0+005e <[^>]*> 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e.s b/gas/testsuite/gas/mips/mips16e.s
new file mode 100644
index 0000000..72e2d09
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.s
@@ -0,0 +1,58 @@
+# Test the mips16e instruction set.
+
+	.set	mips16
+	.text
+stuff:
+	# explicit compact jumps
+	jalrc	$2
+	jalrc	$31,$2
+	jrc	$31
+	jrc	$2
+	
+	# these jumps should all be converted to compact versions
+	jalr	$2
+	jalr	$31,$2
+	jal	$2
+	jal	$31,$2
+	jr	$31
+	jr	$2
+	j	$31
+	j	$2
+	
+	# make sure unconditional jumps don't swap with compact jumps
+	# and vice versa.
+	jalr	$2
+	.set	noreorder
+	jal	foo		# mustn't swap with previous jalr
+	addu	$4,$2,1
+	.set	reorder
+	jalr	$2
+	jal	foo
+	
+	move	$4,$2
+1:	jal	$2		# can't swap with move
+		
+	move	$4,$2
+1:	jr	$2		# can't swap with move
+	
+	move	$4,$2
+1:	jr	$31		# can't swap with move
+	
+	seb	$4
+	seh	$4
+	zeb	$4
+	zeh	$4
+
+	save	$31,8
+	save	$31,128
+	save	$31,$16,16
+	save	$31,$16-$17,16
+	save	$31,$17,120
+	save	$31,$16,136
+	save	$4,$31,$16-$17,16
+	save	$4-$5,$31,$16,$18,$19,$20,16
+	save	$4-$6,$31,$16-$20,16
+	save	$4-$7,$31,$17,$18-$30,16
+	save	$4-$5,$31,$16,$18,$19,$20,16,$6-$7
+	
+	.p2align 4