* config/tc-arm.c (do_t_strexbh): New.

	(insns): Update accordingly.

	* gas/arm/strex-bad-t.d: New testcase.
	* gas/arm/strex-bad-t.s: Likewise.
	* gas/arm/strex-bad-t.l: Likewise.
	* gas/arm/strex-t.s: Likewise.
	* gas/arm/strex-t.d: Likewise.

8 files changed, 114 insertions, 3 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6b94a0a..74f92c7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2011-08-03  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/tc-arm.c (do_t_strexbh): New.
+	(insns): Update accordingly.
+
 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/13048
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b018b4f..77606a3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8501,6 +8501,21 @@ do_strex (void)
 }
 
 static void
+do_t_strexbh (void)
+{
+  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
+	      || inst.operands[2].postind || inst.operands[2].writeback
+	      || inst.operands[2].immisreg || inst.operands[2].shifted
+	      || inst.operands[2].negative,
+	      BAD_ADDR_MODE);
+
+  constraint (inst.operands[0].reg == inst.operands[1].reg
+	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
+
+  do_rm_rd_rn ();
+}
+
+static void
 do_strexd (void)
 {
   constraint (inst.operands[1].reg % 2 != 0,
@@ -17516,9 +17531,9 @@ static const struct asm_opcode insns[] =
  TCE("ldrexh",	1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
      rd_rn,  rd_rn),
  TCE("strexb",	1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
-     strex, rm_rd_rn),
+     strex, t_strexbh),
  TCE("strexh",	1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
-     strex, rm_rd_rn), 
+     strex, t_strexbh),
  TUF("clrex",	57ff01f, f3bf8f2f, 0, (),			      noargs, noargs),
 
 #undef  ARM_VARIANT
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 28a549f..fe9a5a9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2011-08-03  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* gas/arm/strex-bad-t.d: New testcase.
+	* gas/arm/strex-bad-t.s: Likewise.
+	* gas/arm/strex-bad-t.l: Likewise.
+	* gas/arm/strex-t.s: Likewise.
+	* gas/arm/strex-t.d: Likewise.
+
 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/13048
@@ -17,7 +25,7 @@
 	PR gas/13046
 	* gas/i386/x86-64-branch.s: Add tests for direct branch.
 	* gas/i386/x86-64-branch.d: Updated.
-	* gas/i386/ilp32/x86-64-branch.d: Likewise. 
+	* gas/i386/ilp32/x86-64-branch.d: Likewise.
 
 2011-07-29  Nick Clifton  <nickc@redhat.com>
 
diff --git a/gas/testsuite/gas/arm/strex-bad-t.d b/gas/testsuite/gas/arm/strex-bad-t.d
new file mode 100644
index 0000000..f5ec4c5
--- /dev/null
+++ b/gas/testsuite/gas/arm/strex-bad-t.d
@@ -0,0 +1,3 @@
+# name: Bad addressing modes STREXH/STREXB. - THUMB
+# error-output: strex-bad-t.l
+
diff --git a/gas/testsuite/gas/arm/strex-bad-t.l b/gas/testsuite/gas/arm/strex-bad-t.l
new file mode 100644
index 0000000..a490096
--- /dev/null
+++ b/gas/testsuite/gas/arm/strex-bad-t.l
@@ -0,0 +1,24 @@
+[^:]*: Assembler messages:
+[^:]*:7: Error: r15 not allowed here -- `strexh r0,r1,#0x04'
+[^:]*:8: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2\],#0x04'
+[^:]*:9: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,#\+0x00\]!'
+[^:]*:10: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,r3\]'
+[^:]*:11: Error: registers may not be the same -- `strexh r0,r0,\[r1]'
+[^:]*:12: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,#-0x04\]'
+[^:]*:13: Error: r15 not allowed here -- `strexh r0,r1,\[r15\]'
+[^:]*:14: Error: r13 not allowed here -- `strexh r0,r13,\[r1\]'
+[^:]*:15: Error: r15 not allowed here -- `strexh r0,r15,\[r1\]'
+[^:]*:16: Error: r13 not allowed here -- `strexh r13,r0,\[r1\]'
+[^:]*:17: Error: r15 not allowed here -- `strexh r15,r0,\[r1\]'
+[^:]*:21: Error: r15 not allowed here -- `strexb r0,r1,#0x04'
+[^:]*:22: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2\],#0x04'
+[^:]*:23: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,#\+0x00\]!'
+[^:]*:24: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,r3\]'
+[^:]*:25: Error: registers may not be the same -- `strexb r0,r0,\[r1]'
+[^:]*:26: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,#-0x04\]'
+[^:]*:27: Error: r15 not allowed here -- `strexb r0,r1,\[r15\]'
+[^:]*:28: Error: r13 not allowed here -- `strexb r0,r13,\[r1\]'
+[^:]*:29: Error: r15 not allowed here -- `strexb r0,r15,\[r1\]'
+[^:]*:30: Error: r13 not allowed here -- `strexb r13,r0,\[r1\]'
+[^:]*:31: Error: r15 not allowed here -- `strexb r15,r0,\[r1\]'
+
diff --git a/gas/testsuite/gas/arm/strex-bad-t.s b/gas/testsuite/gas/arm/strex-bad-t.s
new file mode 100644
index 0000000..1466ca5
--- /dev/null
+++ b/gas/testsuite/gas/arm/strex-bad-t.s
@@ -0,0 +1,32 @@
+.syntax unified
+
+.thumb
+
+@ strexh
+
+strexh r0, r1, #0x04
+strexh r0, r1, [r2], #0x04
+strexh r0, r1, [r2, #+0x00]!
+strexh r0, r1, [r2, r3]
+strexh r0, r0, [r1]
+strexh r0, r1, [r2, #-0x04]
+strexh r0, r1, [r15]
+strexh r0, r13, [r1]
+strexh r0, r15, [r1]
+strexh r13, r0, [r1]
+strexh r15, r0, [r1]
+
+@ strexb
+
+strexb r0, r1, #0x04
+strexb r0, r1, [r2], #0x04
+strexb r0, r1, [r2, #+0x00]!
+strexb r0, r1, [r2, r3]
+strexb r0, r0, [r1]
+strexb r0, r1, [r2, #-0x04]
+strexb r0, r1, [r15]
+strexb r0, r13, [r1]
+strexb r0, r15, [r1]
+strexb r13, r0, [r1]
+strexb r15, r0, [r1]
+
diff --git a/gas/testsuite/gas/arm/strex-t.d b/gas/testsuite/gas/arm/strex-t.d
new file mode 100644
index 0000000..c38eda6
--- /dev/null
+++ b/gas/testsuite/gas/arm/strex-t.d
@@ -0,0 +1,14 @@
+# name: STREXH/STREXB. - Thumb
+# objdump: -dr --prefix-address --show-raw-insn
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+00 <[^>]+> e8c2 1f50 	strexh	r0, r1, \[r2\]
+0+04 <[^>]+> e8c2 1f50 	strexh	r0, r1, \[r2\]
+0+08 <[^>]+> e8cd 1f50 	strexh	r0, r1, \[sp\]
+0+0c <[^>]+> e8c2 1f40 	strexb	r0, r1, \[r2\]
+0+10 <[^>]+> e8c2 1f40 	strexb	r0, r1, \[r2\]
+0+14 <[^>]+> e8cd 1f40 	strexb	r0, r1, \[sp\]
+
diff --git a/gas/testsuite/gas/arm/strex-t.s b/gas/testsuite/gas/arm/strex-t.s
new file mode 100644
index 0000000..d8cddfc
--- /dev/null
+++ b/gas/testsuite/gas/arm/strex-t.s
@@ -0,0 +1,10 @@
+.syntax unified
+.thumb
+	strexh r0, r1, [r2]
+	strexh r0, r1, [r2, #+0x00]
+	strexh r0, r1, [r13]
+
+	strexb r0, r1, [r2]
+	strexb r0, r1, [r2, #+0x00]
+	strexb r0, r1, [r13]
+