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| author | DJ Delorie <dj@redhat.com> | 2013-08-23 21:29:27 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2013-08-23 21:29:27 +0000 |
| commit | 664a88c6c25f4158a99c4be423cfd94a29686f7b (patch) | |
| tree | 0c139484ad4b541a71b3ce4a18b97ef6206dc0e4 /gas | |
| parent | f8222080f6f2dada74ea43ee0b0b0ab7bff4b2a5 (diff) | |
| download | fsf-binutils-gdb-664a88c6c25f4158a99c4be423cfd94a29686f7b.zip fsf-binutils-gdb-664a88c6c25f4158a99c4be423cfd94a29686f7b.tar.gz fsf-binutils-gdb-664a88c6c25f4158a99c4be423cfd94a29686f7b.tar.bz2 | |
* config/rx-parse.y: Rearrange the components of a bison grammar to issue
assembler errors at correct position.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/rx-parse.y | 16 |
2 files changed, 15 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 679a7d5..d815e5e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com> + + * config/rx-parse.y: Rearrange the components of a bison grammar to issue + assembler errors at correct position. + 2013-08-23 Yuri Chornoivan <yurchor@ukr.net> PR binutils/15834 diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y index 09e3e84..3933e6b 100644 --- a/gas/config/rx-parse.y +++ b/gas/config/rx-parse.y @@ -882,15 +882,19 @@ op_shift float2_op - : '#' EXPR ',' REG - { rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); } + : { rx_check_float_support (); } + '#' EXPR ',' REG + { id24 (2, 0x72, sub_op << 4); F ($5, 20, 4); O4 ($3); } | float2_op_ni ; + float2_op_ni - : REG ',' REG - { rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); } - | disp '[' REG ']' opt_l ',' REG - { rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); } + : { rx_check_float_support (); } + REG ',' REG + { id24 (1, 0x83 + (sub_op << 2), 0); F ($2, 16, 4); F ($4, 20, 4); } + | { rx_check_float_support (); } + disp '[' REG ']' opt_l ',' REG + { id24 (1, 0x80 + (sub_op << 2), 0); F ($4, 16, 4); F ($8, 20, 4); DSP ($2, 14, LSIZE); } ; /* ====================================================================== */ |