Add support for Intel CET instructions

Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

10 files changed, 213 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 654b3cb..f9af65d6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,17 @@
 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* config/tc-i386.c (cpu_arch): Add .cet.
+	* doc/c-i386.texi: Document cet.
+	* testsuite/gas/i386/cet-intel.d: New file.
+	* testsuite/gas/i386/cet.d: Likewise.
+	* testsuite/gas/i386/cet.s: Likewise.
+	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet.s: Likewise.
+	* testsuite/gas/i386/i386.exp: Run Intel CET tests.
+
+2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
 	* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 12b3032..7deacad 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -978,6 +978,8 @@ static const arch_entry cpu_arch[] =
     CPU_RDPID_FLAGS, 0 },
   { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
     CPU_PTWRITE_FLAGS, 0 },
+  { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
+    CPU_CET_FLAGS, 0 },
 };
 
 static const noarch_entry cpu_noarch[] =
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 2cbffb9..0733587 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -167,6 +167,7 @@ accept various extension mnemonics.  For example,
 @code{sha},
 @code{rdpid},
 @code{ptwrite},
+@code{cet},
 @code{prefetchwt1},
 @code{clflushopt},
 @code{se1},
@@ -1198,6 +1199,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
 @item @samp{.avx512_vpopcntdq} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
+@item @samp{.cet}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/gas/i386/cet-intel.d b/gas/testsuite/gas/i386/cet-intel.d
new file mode 100644
index 0000000..a5f5533
--- /dev/null
+++ b/gas/testsuite/gas/i386/cet-intel.d
@@ -0,0 +1,31 @@
+#source: cet.s
+#as: -J
+#objdump: -dw -Mintel
+#name: i386 CET (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 29          	rstorssp QWORD PTR \[ecx\]
+ +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  \[edx\+eax\*1\],eax
+ +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[eax\]
+ +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy QWORD PTR \[esp\+eax\*1\]
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp QWORD PTR \[ecx\+eax\*1\]
+ +[a-f0-9]+:	0f 38 f6 02          	wrssd  \[edx\],eax
+ +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[eax\]
+ +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy QWORD PTR \[esp\+eax\*1\]
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+#pass
diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d
new file mode 100644
index 0000000..bb356e4
--- /dev/null
+++ b/gas/testsuite/gas/i386/cet.d
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: i386 CET
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 29          	rstorssp \(%ecx\)
+ +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  %eax,\(%edx,%eax,1\)
+ +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%eax\)
+ +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy \(%esp,%eax,1\)
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp \(%ecx,%eax,1\)
+ +[a-f0-9]+:	0f 38 f6 02          	wrssd  %eax,\(%edx\)
+ +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%eax\)
+ +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy \(%esp,%eax,1\)
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+#pass
diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s
new file mode 100644
index 0000000..deb659d
--- /dev/null
+++ b/gas/testsuite/gas/i386/cet.s
@@ -0,0 +1,25 @@
+# Check CET instructions
+	.text
+_start:
+	incsspd
+	rdsspd %ecx
+	savessp
+	rstorssp (%ecx)
+	wrssd %eax, (%edx, %eax)
+	wrussd %edx, (%edi, %ebp)
+	setssbsy (%eax)
+	clrssbsy (%esp, %eax)
+	endbr64
+	endbr32
+
+	.intel_syntax noprefix
+	incsspd
+	rdsspd ecx
+	savessp
+	rstorssp QWORD PTR [ecx + eax]
+	wrssd [edx],eax
+	wrussd [edi + ebp],edx
+	setssbsy QWORD PTR [eax]
+	clrssbsy QWORD PTR [esp + eax]
+	endbr64
+	endbr32
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 10fe71c..cc5917a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -382,6 +382,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_list_test "avx512vl-1" "-al"
     run_list_test "avx512vl-2" "-al"
     run_dump_test "fpu-bad"
+    run_dump_test "cet"
+    run_dump_test "cet-intel"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -799,6 +801,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_list_test "x86-64-avx512vl-1" "-al"
     run_list_test "x86-64-avx512vl-2" "-al"
     run_dump_test "x86-64-opcode-bad"
+    run_dump_test "x86-64-cet"
+    run_dump_test "x86-64-cet-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/x86-64-cet-intel.d b/gas/testsuite/gas/i386/x86-64-cet-intel.d
new file mode 100644
index 0000000..07e666f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d
@@ -0,0 +1,38 @@
+#source: x86-64-cet.s
+#objdump: -dw -Mintel
+#name: x86-64 CET (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
+ +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp QWORD PTR \[r12\]
+ +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  \[r12\],eax
+ +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
+ +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd \[r12\],eax
+ +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq \[rbx\+rax\*1\],rcx
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[rax\]
+ +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy QWORD PTR \[rsi\+r12\*1\]
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
+ +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp QWORD PTR \[r12\]
+ +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  \[r12\],eax
+ +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
+ +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd \[r12\],eax
+ +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq \[rbx\+rax\*1\],rcx
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy QWORD PTR \[rax\]
+ +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy QWORD PTR \[rsi\+r12\*1\]
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-cet.d b/gas/testsuite/gas/i386/x86-64-cet.d
new file mode 100644
index 0000000..7e5b717
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cet.d
@@ -0,0 +1,37 @@
+#objdump: -dw
+#name: x86-64 CET
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
+ +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp \(%r12\)
+ +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  %eax,\(%r12\)
+ +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
+ +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd %eax,\(%r12\)
+ +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq %rcx,\(%rbx,%rax,1\)
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%rax\)
+ +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy \(%rsi,%r12,1\)
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
+ +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
+ +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
+ +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
+ +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp \(%r12\)
+ +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  %eax,\(%r12\)
+ +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
+ +[a-f0-9]+:	66 41 0f 38 f5 04 24 	wrussd %eax,\(%r12\)
+ +[a-f0-9]+:	66 48 0f 38 f5 0c 03 	wrussq %rcx,\(%rbx,%rax,1\)
+ +[a-f0-9]+:	f3 0f ae 28          	setssbsy \(%rax\)
+ +[a-f0-9]+:	f3 42 0f ae 34 26    	clrssbsy \(%rsi,%r12,1\)
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-cet.s b/gas/testsuite/gas/i386/x86-64-cet.s
new file mode 100644
index 0000000..15a28d7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cet.s
@@ -0,0 +1,33 @@
+# Check 64bit CET instructions
+	.text
+_start:
+	incsspd
+	incsspq
+	rdsspd %r12d
+	rdsspq %rax
+	savessp
+	rstorssp (%r12)
+	wrssd %eax, (%r12)
+	wrssq %rdx, (%rcx, %r15)
+	wrussd %eax, (%r12)
+	wrussq %rcx, (%rbx, %rax)
+	setssbsy (%rax)
+	clrssbsy (%rsi, %r12)
+	endbr64
+	endbr32
+
+	.intel_syntax noprefix
+	incsspd
+	incsspq
+	rdsspd r12d
+	rdsspq rax
+	savessp
+	rstorssp QWORD PTR [r12]
+	wrssd [r12],eax
+	wrssq [rcx+r15],rdx
+	wrussd [r12],eax
+	wrussq [rbx+rax],rcx
+	setssbsy QWORD PTR [rax]
+	clrssbsy QWORD PTR [rsi+r12]
+	endbr64
+	endbr32