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author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-02-02 10:06:15 +0900 |
---|---|---|
committer | Nelson Chu <nelson@rivosinc.com> | 2022-08-30 17:46:11 +0800 |
commit | 0938b032daa52129b4215d8e0eedb6c9804f5280 (patch) | |
tree | f66e988ae822b77aa3b7757b65b1850c387b2205 /gas | |
parent | 1c04f72368c925288a6f1b1abb0dbc31a60d2f49 (diff) | |
download | fsf-binutils-gdb-0938b032daa52129b4215d8e0eedb6c9804f5280.zip fsf-binutils-gdb-0938b032daa52129b4215d8e0eedb6c9804f5280.tar.gz fsf-binutils-gdb-0938b032daa52129b4215d8e0eedb6c9804f5280.tar.bz2 |
RISC-V: Add 'Zmmul' extension in assembler.
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/testsuite/gas/riscv/attribute-09.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-32.d | 18 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-64.d | 23 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l | 14 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/m-ext.s | 21 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/option-arch-02.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/zmmul-32.d | 14 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/zmmul-64.d | 15 |
15 files changed, 143 insertions, 2 deletions
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d index fc87f82..c92dc97 100644 --- a/gas/testsuite/gas/riscv/attribute-09.d +++ b/gas/testsuite/gas/riscv/attribute-09.d @@ -3,4 +3,4 @@ #source: empty.s Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0" + Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0_zmmul1p0" diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d new file mode 100644 index 0000000..fe2ef9a --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-32.d @@ -0,0 +1,18 @@ +#as: -march=rv32im +#source: m-ext.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d new file mode 100644 index 0000000..05099b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-64.d @@ -0,0 +1,23 @@ +#as: -march=rv64im -defsym rv64=1 +#source: m-ext.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5c53b[ ]+divw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5d53b[ ]+divuw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5e53b[ ]+remw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5f53b[ ]+remuw[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d new file mode 100644 index 0000000..3c4fc9a --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d @@ -0,0 +1,4 @@ +#as: -march=rv64i -defsym rv64=1 +#source: m-ext.s +#objdump: -d +#error_output: m-ext-fail-noarch-64.l diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l new file mode 100644 index 0000000..db9c8fb --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l @@ -0,0 +1,14 @@ +.*Assembler messages: +.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required +.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required +.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required +.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required +.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `mulw a0,a1,a2', extension `m' or `zmmul' required +.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d new file mode 100644 index 0000000..54f8b82 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d @@ -0,0 +1,4 @@ +#as: -march=rv32im -defsym rv64=1 +#source: m-ext.s +#objdump: -d +#error_output: m-ext-fail-xlen-32.l diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l new file mode 100644 index 0000000..d65ca49 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l @@ -0,0 +1,6 @@ +.*Assembler messages: +.*: Error: unrecognized opcode `mulw a0,a1,a2' +.*: Error: unrecognized opcode `divw a0,a1,a2' +.*: Error: unrecognized opcode `divuw a0,a1,a2' +.*: Error: unrecognized opcode `remw a0,a1,a2' +.*: Error: unrecognized opcode `remuw a0,a1,a2' diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d new file mode 100644 index 0000000..c164fa9 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d @@ -0,0 +1,4 @@ +#as: -march=rv32i_zmmul +#source: m-ext.s +#objdump: -d +#error_output: m-ext-fail-zmmul-32.l diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l new file mode 100644 index 0000000..0151001 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l @@ -0,0 +1,5 @@ +.*Assembler messages: +.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d new file mode 100644 index 0000000..f736d9c --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d @@ -0,0 +1,4 @@ +#as: -march=rv64i_zmmul -defsym rv64=1 +#source: m-ext.s +#objdump: -d +#error_output: m-ext-fail-zmmul-64.l diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l new file mode 100644 index 0000000..7779973 --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l @@ -0,0 +1,9 @@ +.*Assembler messages: +.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required +.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s new file mode 100644 index 0000000..68baf2a --- /dev/null +++ b/gas/testsuite/gas/riscv/m-ext.s @@ -0,0 +1,21 @@ +target: + mul a0, a1, a2 + mulh a0, a1, a2 + mulhsu a0, a1, a2 + mulhu a0, a1, a2 +.ifndef zmmul + div a0, a1, a2 + divu a0, a1, a2 + rem a0, a1, a2 + remu a0, a1, a2 +.endif + +.ifdef rv64 + mulw a0, a1, a2 +.ifndef zmmul + divw a0, a1, a2 + divuw a0, a1, a2 + remw a0, a1, a2 + remuw a0, a1, a2 +.endif +.endif diff --git a/gas/testsuite/gas/riscv/option-arch-02.d b/gas/testsuite/gas/riscv/option-arch-02.d index 9ca013e..3c27419 100644 --- a/gas/testsuite/gas/riscv/option-arch-02.d +++ b/gas/testsuite/gas/riscv/option-arch-02.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_xvendor32x3p0" + Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0" #... diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d new file mode 100644 index 0000000..c9cf56a --- /dev/null +++ b/gas/testsuite/gas/riscv/zmmul-32.d @@ -0,0 +1,14 @@ +#as: -march=rv32im -defsym zmmul=1 +#source: m-ext.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d new file mode 100644 index 0000000..67ef360 --- /dev/null +++ b/gas/testsuite/gas/riscv/zmmul-64.d @@ -0,0 +1,15 @@ +#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1 +#source: m-ext.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2 |