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author | Jan Beulich <jbeulich@novell.com> | 2017-11-15 08:48:51 +0100 |
---|---|---|
committer | Jan Beulich <jbeulich@suse.com> | 2017-11-15 08:48:51 +0100 |
commit | 0645f0a2a75ad77d9786595978591d3f302f9647 (patch) | |
tree | dbb506276f9cd08824e99995a4a471403b9d56ee /gas | |
parent | 99847db8ea741f895d79b9312114c13ccb660d83 (diff) | |
download | fsf-binutils-gdb-0645f0a2a75ad77d9786595978591d3f302f9647.zip fsf-binutils-gdb-0645f0a2a75ad77d9786595978591d3f302f9647.tar.gz fsf-binutils-gdb-0645f0a2a75ad77d9786595978591d3f302f9647.tar.bz2 |
x86-64: don't allow use of %axl as accumulator
Just like %cxl can't be used as shift count register. Otherwise for
consistency %cxl would need to gain "ShiftCount" and use of both ought
to properly cause REX prefixes to be emitted.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 12 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/i386.exp | 1 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/ilp32/x86-64-reg.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-reg-bad.l | 20 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-reg-bad.s | 11 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-reg-intel.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-reg.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-reg.s | 9 |
9 files changed, 85 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index f927393..66bc034 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,15 @@ +2017-11-15 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/x86-64-reg.s: Add extended byte reg tests. + * testsuite/gas/i386/x86-64-reg.d, + testsuite/gas/i386/x86-64-reg-intel.d, + testsuite/gas/i386/ilp32/x86-64-reg.d, + testsuite/gas/i386/ilp32/x86-64-reg-intel.d: Adjust + expectations. + + * testsuite/gas/i386/x86-64-reg-bad.{s,l}: New. + * testsuite/gas/i386/i386.exp: Run new test. + 2017-11-14 Jim Wilson <jimw@sifive.com> * testsuite/gas/lns/lns.exp (lns-common-1): Add riscv*-*-* to alt list. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 1662d9c..7a8b642 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -628,6 +628,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-mem" run_dump_test "x86-64-mem-intel" run_dump_test "x86-64-reg" + run_list_test "x86-64-reg-bad" "-al" run_dump_test "x86-64-reg-intel" run_dump_test "x86-64-sib" run_dump_test "x86-64-sib-intel" diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d index 839df9c..99d79d5 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-reg-intel.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq xmm10,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq xmm10,0x2 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add al,0x1 +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add cl,0x1 +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add dl,0x1 +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add bl,0x1 +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add spl,0x1 +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add bpl,0x1 +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add sil,0x1 +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add dil,0x1 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2 diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-reg.d b/gas/testsuite/gas/i386/ilp32/x86-64-reg.d index ca17e40..99e67fb 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-reg.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-reg.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq \$0x2,%xmm10 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq \$0x2,%xmm10 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add \$0x1,%al +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add \$0x1,%cl +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add \$0x1,%dl +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add \$0x1,%bl +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add \$0x1,%spl +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add \$0x1,%bpl +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add \$0x1,%sil +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add \$0x1,%dil [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6 diff --git a/gas/testsuite/gas/i386/x86-64-reg-bad.l b/gas/testsuite/gas/i386/x86-64-reg-bad.l new file mode 100644 index 0000000..585f1e1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-reg-bad.l @@ -0,0 +1,20 @@ +.*: Assembler messages: +.*:6: Error: .* mismatch for `div' +.*:7: Error: .* mismatch for `in' +.*:8: Error: .* mismatch for `lods' +.*:9: Error: .* mismatch for `movabs' +.*:10: Error: .* mismatch for `shl' +GAS LISTING .* + + +[ ]*[1-9][0-9]*[ ]+\# Check %axl / %cxl aren't permitted as accumulator / shift count +[ ]*[1-9][0-9]*[ ]+ +[ ]*[1-9][0-9]*[ ]+\.text +[ ]*[1-9][0-9]*[ ]+reg: +[ ]*[1-9][0-9]*[ ]+\?* 4080C001[ ]+add \$1, %axl +[ ]*[1-9][0-9]*[ ]+div %bl, %axl +[ ]*[1-9][0-9]*[ ]+in %dx, %axl +[ ]*[1-9][0-9]*[ ]+lods \(%rsi\), %axl +[ ]*[1-9][0-9]*[ ]+movabs -1, %axl +[ ]*[1-9][0-9]*[ ]+shl %cxl, %eax +[ ]*[1-9][0-9]*[ ]+\?* 40F6C001[ ]+test \$1, %axl diff --git a/gas/testsuite/gas/i386/x86-64-reg-bad.s b/gas/testsuite/gas/i386/x86-64-reg-bad.s new file mode 100644 index 0000000..d7e0c7c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-reg-bad.s @@ -0,0 +1,11 @@ +# Check %axl / %cxl aren't permitted as accumulator / shift count + + .text +reg: + add $1, %axl + div %bl, %axl + in %dx, %axl + lods (%rsi), %axl + movabs -1, %axl + shl %cxl, %eax + test $1, %axl diff --git a/gas/testsuite/gas/i386/x86-64-reg-intel.d b/gas/testsuite/gas/i386/x86-64-reg-intel.d index c04645b..00120b7 100644 --- a/gas/testsuite/gas/i386/x86-64-reg-intel.d +++ b/gas/testsuite/gas/i386/x86-64-reg-intel.d @@ -26,6 +26,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq xmm10,0x2 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq xmm10,0x2 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add al,0x1 +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add cl,0x1 +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add dl,0x1 +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add bl,0x1 +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add spl,0x1 +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add bpl,0x1 +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add sil,0x1 +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add dil,0x1 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2 diff --git a/gas/testsuite/gas/i386/x86-64-reg.d b/gas/testsuite/gas/i386/x86-64-reg.d index fb560d1..292a827 100644 --- a/gas/testsuite/gas/i386/x86-64-reg.d +++ b/gas/testsuite/gas/i386/x86-64-reg.d @@ -25,6 +25,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6 [ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq \$0x2,%xmm10 [ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq \$0x2,%xmm10 +[ ]*[a-f0-9]+: 40 80 c0 01[ ]+add \$0x1,%al +[ ]*[a-f0-9]+: 40 80 c1 01[ ]+add \$0x1,%cl +[ ]*[a-f0-9]+: 40 80 c2 01[ ]+add \$0x1,%dl +[ ]*[a-f0-9]+: 40 80 c3 01[ ]+add \$0x1,%bl +[ ]*[a-f0-9]+: 40 80 c4 01[ ]+add \$0x1,%spl +[ ]*[a-f0-9]+: 40 80 c5 01[ ]+add \$0x1,%bpl +[ ]*[a-f0-9]+: 40 80 c6 01[ ]+add \$0x1,%sil +[ ]*[a-f0-9]+: 40 80 c7 01[ ]+add \$0x1,%dil [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2 [ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6 diff --git a/gas/testsuite/gas/i386/x86-64-reg.s b/gas/testsuite/gas/i386/x86-64-reg.s index 6dcaba5..69ac24b 100644 --- a/gas/testsuite/gas/i386/x86-64-reg.s +++ b/gas/testsuite/gas/i386/x86-64-reg.s @@ -21,6 +21,15 @@ psllq $2, %mm6 psllq $2, %xmm10 pslldq $2, %xmm10 + add $1, %axl + add $1, %cxl + add $1, %dxl + add $1, %bxl + add $1, %spl + add $1, %bpl + add $1, %sil + add $1, %dil + .intel_syntax noprefix psrlw mm6, 2 psrlw xmm2, 2 |