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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:02:06 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:02:24 +0000 |
commit | 01a4d0822025084609380fb989d43bda0667db72 (patch) | |
tree | 5c1888e350164f67afae5b11ab70b82fa4a353bf /gas | |
parent | 1cad938de57a1577e5fe4b4afcabe889a8b9b9d7 (diff) | |
download | fsf-binutils-gdb-01a4d0822025084609380fb989d43bda0667db72.zip fsf-binutils-gdb-01a4d0822025084609380fb989d43bda0667db72.tar.gz fsf-binutils-gdb-01a4d0822025084609380fb989d43bda0667db72.tar.bz2 |
aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions
This patch is adding new loads and stores defined by SME instructions.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_address): New parser.
(parse_sme_za_hv_tiles_operand_with_braces): New parser.
(parse_sme_za_array): New parser.
(output_operand_error_record): Print error details if
present.
(parse_operands): Support new operands.
* testsuite/gas/aarch64/sme-5-illegal.d: New test.
* testsuite/gas/aarch64/sme-5-illegal.l: New test.
* testsuite/gas/aarch64/sme-5-illegal.s: New test.
* testsuite/gas/aarch64/sme-5.d: New test.
* testsuite/gas/aarch64/sme-5.s: New test.
* testsuite/gas/aarch64/sme-6-illegal.d: New test.
* testsuite/gas/aarch64/sme-6-illegal.l: New test.
* testsuite/gas/aarch64/sme-6-illegal.s: New test.
* testsuite/gas/aarch64/sme-6.d: New test.
* testsuite/gas/aarch64/sme-6.s: New test.
* testsuite/gas/aarch64/sme-7-illegal.d: New test.
* testsuite/gas/aarch64/sme-7-illegal.l: New test.
* testsuite/gas/aarch64/sme-7-illegal.s: New test.
* testsuite/gas/aarch64/sme-7.d: New test.
* testsuite/gas/aarch64/sme-7.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands.
(enum aarch64_insn_class): Added sme_ldr and sme_str.
(AARCH64_OPDE_UNTIED_IMMS): New operand error kind.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter.
(aarch64_ins_sme_za_list): New inserter.
(aarch64_ins_sme_za_array): New inserter.
(aarch64_ins_sme_addr_ri_u4xvl): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added
ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor.
(aarch64_ext_sme_za_list): New extractor.
(aarch64_ext_sme_za_array): New extractor.
(aarch64_ext_sme_addr_ri_u4xvl): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added
ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl.
* aarch64-opc.c (operand_general_constraint_met_p):
(aarch64_match_operands_constraint): Handle sme_ldr, sme_str
and sme_misc.
(aarch64_print_operand): New operands supported.
* aarch64-tbl.h (OP_SVE_QUU): New qualifier.
(OP_SVE_QZU): New qualifier.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/config/tc-aarch64.c | 115 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5-illegal.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5-illegal.l | 51 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5-illegal.s | 52 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5.d | 93 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5.s | 101 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6-illegal.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6-illegal.l | 45 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6-illegal.s | 46 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6.d | 85 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6.s | 86 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7-illegal.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7-illegal.l | 33 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7-illegal.s | 39 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7.d | 27 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7.s | 27 |
16 files changed, 801 insertions, 8 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 15bfe8e..d45b903 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4460,6 +4460,38 @@ parse_sme_za_hv_tiles_operand (char **str, return regno; } + +static int +parse_sme_za_hv_tiles_operand_with_braces (char **str, + enum sme_hv_slice *slice_indicator, + int *vector_select_register, + int *imm, + aarch64_opnd_qualifier_t *qualifier) +{ + int regno; + + if (!skip_past_char (str, '{')) + { + set_syntax_error (_("expected '{'")); + return PARSE_FAIL; + } + + regno = parse_sme_za_hv_tiles_operand (str, slice_indicator, + vector_select_register, imm, + qualifier); + + if (regno == PARSE_FAIL) + return PARSE_FAIL; + + if (!skip_past_char (str, '}')) + { + set_syntax_error (_("expected '}'")); + return PARSE_FAIL; + } + + return regno; +} + /* Parse list of up to eight 64-bit element tile names separated by commas in SME's ZERO instruction: @@ -4558,6 +4590,45 @@ parse_sme_list_of_64bit_tiles (char **str) return regno; } +/* Parse ZA array operand used in e.g. STR and LDR instruction. + Operand format: + + ZA[<Wv>, <imm>] + ZA[<Wv>, #<imm>] + + Function returns <Wv> or PARSE_FAIL. +*/ +static int +parse_sme_za_array (char **str, int *imm) +{ + char *p, *q; + int regno; + int64_t imm_value; + + p = q = *str; + while (ISALPHA (*q)) + q++; + + if ((q - p != 2) || strncasecmp ("za", p, q - p) != 0) + { + set_syntax_error (_("expected ZA array")); + return PARSE_FAIL; + } + + if (! parse_sme_za_hv_tiles_operand_index (&q, ®no, &imm_value)) + return PARSE_FAIL; + + if (imm_value < 0 || imm_value > 15) + { + set_syntax_error (_("offset out of range")); + return PARSE_FAIL; + } + + *imm = imm_value; + *str = q; + return regno; +} + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. Returns the encoding for the option, or PARSE_FAIL. @@ -5364,9 +5435,15 @@ output_operand_error_record (const operand_error_record *record, char *str) } break; + case AARCH64_OPDE_UNTIED_IMMS: + handler (_("operand %d must have the same immediate value " + "as operand 1 -- `%s'"), + detail->index + 1, str); + break; + case AARCH64_OPDE_UNTIED_OPERAND: handler (_("operand %d must be the same register as operand 1 -- `%s'"), - detail->index + 1, str); + detail->index + 1, str); break; case AARCH64_OPDE_OUT_OF_RANGE: @@ -6958,6 +7035,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ADDR_RI_S4x16: case AARCH64_OPND_SVE_ADDR_RI_S4x32: case AARCH64_OPND_SVE_ADDR_RI_S4xVL: + case AARCH64_OPND_SME_ADDR_RI_U4xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL: @@ -7013,11 +7091,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; } goto regoff_addr; - + case AARCH64_OPND_SVE_ADDR_RR: case AARCH64_OPND_SVE_ADDR_RR_LSL1: case AARCH64_OPND_SVE_ADDR_RR_LSL2: case AARCH64_OPND_SVE_ADDR_RR_LSL3: + case AARCH64_OPND_SVE_ADDR_RR_LSL4: case AARCH64_OPND_SVE_ADDR_RX: case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: @@ -7273,20 +7352,29 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SME_ZA_HV_idx_src: case AARCH64_OPND_SME_ZA_HV_idx_dest: + case AARCH64_OPND_SME_ZA_HV_idx_ldstr: { - enum sme_hv_slice vector_indicator; + enum sme_hv_slice slice_indicator; int vector_select_register; int imm; - val = parse_sme_za_hv_tiles_operand (&str, &vector_indicator, - &vector_select_register, - &imm, - &qualifier); + + if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr) + val = parse_sme_za_hv_tiles_operand_with_braces (&str, + &slice_indicator, + &vector_select_register, + &imm, + &qualifier); + else + val = parse_sme_za_hv_tiles_operand (&str, &slice_indicator, + &vector_select_register, + &imm, + &qualifier); if (val == PARSE_FAIL) goto failure; info->za_tile_vector.regno = val; info->za_tile_vector.index.regno = vector_select_register; info->za_tile_vector.index.imm = imm; - info->za_tile_vector.v = vector_indicator; + info->za_tile_vector.v = slice_indicator; info->qualifier = qualifier; break; } @@ -7298,6 +7386,17 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->imm.value = val; break; + case AARCH64_OPND_SME_ZA_array: + { + int imm; + val = parse_sme_za_array (&str, &imm); + if (val == PARSE_FAIL) + goto failure; + info->za_tile_vector.index.regno = val; + info->za_tile_vector.index.imm = imm; + break; + } + default: as_fatal (_("unhandled operand code %d"), operands[i]); } diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.d b/gas/testsuite/gas/aarch64/sme-5-illegal.d new file mode 100644 index 0000000..0513dc0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme-5-illegal.s +#error_output: sme-5-illegal.l diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l new file mode 100644 index 0000000..c2f8bc9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -0,0 +1,51 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]' +[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]' +[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {za0h.b\[w12,0\]},p0/z,\[x0,x1,lsl#1\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0h.h\[w12,0\]},p0/z,\[x0,x1,lsl#2\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]' +[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]' diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s new file mode 100644 index 0000000..bf65f6a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s @@ -0,0 +1,52 @@ +/* Scalable Matrix Extension (SME). */ +ld1b {za0h.b[w11, 0]}, p0/z, [x0] +ld1h {za0h.h[w16, 0]}, p0/z, [x0] +ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #3] +ld1w {za3v.s[w15, 3]}, p7/z, [sp, lsl #2] +ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #12] +ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #2] +ld1b {za1h.b[w12, 0]}, p0/z, [x0] +ld1b {za1v.b[w12, 0]}, p0/z, [sp] +ld1b {za1h.b[w12, 0]}, p0/z, [sp, x0] +ld1b {za0v.b[w15, 16]}, p7/z, [x17] +ld1b {za0h.b[w15, 16]}, p7/z, [sp] +ld1b {za0v.b[w15, 16]}, p7/z, [sp, x17] +ld1h {za2v.h[w12, 0]}, p0/z, [x0] +ld1h {za2h.h[w12, 0]}, p0/z, [sp] +ld1h {za2v.h[w12, 0]}, p0/z, [x0, x0, lsl #1] +ld1h {za2h.h[w12, 0]}, p0/z, [sp, x0, lsl #1] +ld1h {za1v.h[w15, 8]}, p7/z, [x17] +ld1h {za1h.h[w15, 8]}, p7/z, [sp] +ld1h {za1v.h[w15, 8]}, p7/z, [x0, x17, lsl #1] +ld1h {za1h.h[w15, 8]}, p7/z, [sp, x17, lsl #1] +ld1w {za4h.s[w12, 0]}, p0/z, [x0] +ld1w {za4v.s[w12, 0]}, p0/z, [sp] +ld1w {za4h.s[w12, 0]}, p0/z, [x0, x0, lsl #2] +ld1w {za4v.s[w12, 0]}, p0/z, [sp, x0, lsl #2] +ld1w {za3h.s[w15, 4]}, p7/z, [x17] +ld1w {za3v.s[w15, 4]}, p7/z, [sp] +ld1w {za3h.s[w15, 4]}, p7/z, [x0, x17, lsl #2] +ld1w {za3v.s[w15, 4]}, p7/z, [sp, x17, lsl #2] +ld1d {za8v.d[w12, 0]}, p0/z, [x0] +ld1d {za8h.d[w12, 0]}, p0/z, [sp] +ld1d {za8v.d[w12, 0]}, p0/z, [x0, x0, lsl #3] +ld1d {za8h.d[w12, 0]}, p0/z, [sp, x0, lsl #3] +ld1d {za7v.d[w15, 2]}, p7/z, [x17] +ld1d {za7h.d[w15, 2]}, p7/z, [sp] +ld1d {za7v.d[w15, 2]}, p7/z, [x0, x17, lsl #3] +ld1d {za7h.d[w15, 2]}, p7/z, [sp, x17, lsl #3] +ld1q {za16v.q[w12]}, p0/z, [x0] +ld1q {za16h.q[w12]}, p0/z, [sp] +ld1q {za16v.q[w12]}, p0/z, [x0, x0, lsl #4] +ld1q {za16h.q[w12]}, p0/z, [sp, x0, lsl #4] +ld1q {za15v.q[w15, 1]}, p7/z, [x17] +ld1q {za15h.q[w15, 1]}, p7/z, [sp] +ld1q {za15v.q[w15, 1]}, p7/z, [x0, x17, lsl #4] +ld1q {za15h.q[w15, 1]}, p7/z, [sp, x17, lsl #4] +/* Illegal operand 3 addressing modes. */ +ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1, lsl #1] +ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1, lsl #2] +ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3] +ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4] +ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1] +ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1] diff --git a/gas/testsuite/gas/aarch64/sme-5.d b/gas/testsuite/gas/aarch64/sme-5.d new file mode 100644 index 0000000..6667534 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-5.d @@ -0,0 +1,93 @@ +#name: SME extension (LD1x instructions) +#as: -march=armv8-a+sme +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: e01f0000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, xzr\] + 4: e01f03e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, xzr\] + 8: e00003e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, x0\] + c: e01f7e2f ld1b {za0h.b\[w15, 15\]}, p7/z, \[x17, xzr\] + 10: e01f7fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, xzr\] + 14: e0117fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, x17\] + 18: e05f0000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] + 1c: e05f03e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] + 20: e0400000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] + 24: e04003e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] + 28: e05f7e2f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] + 2c: e05f7fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] + 30: e0517c0f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] + 34: e0517fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] + 38: e09f0000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] + 3c: e09f03e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] + 40: e0800000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] + 44: e08003e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] + 48: e09f7e2f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] + 4c: e09f7fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] + 50: e0917c0f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] + 54: e0917fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] + 58: e0df0000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] + 5c: e0df03e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] + 60: e0c00000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] + 64: e0c003e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] + 68: e0df7e2f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] + 6c: e0df7fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] + 70: e0d17c0f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] + 74: e0d17fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] + 78: e1df0000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] + 7c: e1df03e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] + 80: e1c00000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] + 84: e1c003e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] + 88: e1df7e2f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] + 8c: e1df7fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] + 90: e1d17c0f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] + 94: e1d17fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] + 98: e01f8000 ld1b {za0v.b\[w12, 0\]}, p0/z, \[x0, xzr\] + 9c: e01f83e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, xzr\] + a0: e00083e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, x0\] + a4: e01ffe2f ld1b {za0v.b\[w15, 15\]}, p7/z, \[x17, xzr\] + a8: e01fffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, xzr\] + ac: e011ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x17\] + b0: e05f8000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] + b4: e05f83e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] + b8: e0408000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] + bc: e04083e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] + c0: e05ffe2f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] + c4: e05fffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] + c8: e051fc0f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] + cc: e051ffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] + d0: e09f8000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] + d4: e09f83e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] + d8: e0808000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] + dc: e08083e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] + e0: e09ffe2f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] + e4: e09fffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] + e8: e091fc0f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] + ec: e091ffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] + f0: e0df8000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] + f4: e0df83e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] + f8: e0c08000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] + fc: e0c083e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] + 100: e0dffe2f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] + 104: e0dfffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] + 108: e0d1fc0f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] + 10c: e0d1ffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] + 110: e1df8000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] + 114: e1df83e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] + 118: e1c08000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] + 11c: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] + 120: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] + 124: e1dfffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] + 128: e1d1fc0f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] + 12c: e1d1ffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] + 130: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] + 134: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] + 138: e000ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x0\] + 13c: e0010000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, x1\] + 140: e0410000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x1, lsl #1\] + 144: e0819c0f ld1w {za3v.s\[w12, 3\]}, p7/z, \[x0, x1, lsl #2\] + 148: e0c10000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x1, lsl #3\] + 14c: e1c18000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x1, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sme-5.s b/gas/testsuite/gas/aarch64/sme-5.s new file mode 100644 index 0000000..e0d79f6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-5.s @@ -0,0 +1,101 @@ +/* SME Extension (LD1x instructions). */ +ld1b {za0h.b[w12, 0]}, p0/z, [x0] +ld1b {za0h.b[w12, 0]}, p0/z, [sp] +ld1b {za0h.b[w12, 0]}, p0/z, [sp, x0] +ld1b {za0h.b[w15, 15]}, p7/z, [x17] +ld1b {za0h.b[w15, 15]}, p7/z, [sp] +ld1b {za0h.b[w15, 15]}, p7/z, [sp, x17] + +ld1h {za0h.h[w12, 0]}, p0/z, [x0] +ld1h {za0h.h[w12, 0]}, p0/z, [sp] +ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1] +ld1h {za0h.h[w12, 0]}, p0/z, [sp, x0, lsl #1] +ld1h {za1h.h[w15, 7]}, p7/z, [x17] +ld1h {za1h.h[w15, 7]}, p7/z, [sp] +ld1h {za1h.h[w15, 7]}, p7/z, [x0, x17, lsl #1] +ld1h {za1h.h[w15, 7]}, p7/z, [sp, x17, lsl #1] + +ld1w {za0h.s[w12, 0]}, p0/z, [x0] +ld1w {za0h.s[w12, 0]}, p0/z, [sp] +ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2] +ld1w {za0h.s[w12, 0]}, p0/z, [sp, x0, lsl #2] +ld1w {za3h.s[w15, 3]}, p7/z, [x17] +ld1w {za3h.s[w15, 3]}, p7/z, [sp] +ld1w {za3h.s[w15, 3]}, p7/z, [x0, x17, lsl #2] +ld1w {za3h.s[w15, 3]}, p7/z, [sp, x17, lsl #2] + +ld1d {za0h.d[w12, 0]}, p0/z, [x0] +ld1d {za0h.d[w12, 0]}, p0/z, [sp] +ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3] +ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #3] +ld1d {za7h.d[w15, 1]}, p7/z, [x17] +ld1d {za7h.d[w15, 1]}, p7/z, [sp] +ld1d {za7h.d[w15, 1]}, p7/z, [x0, x17, lsl #3] +ld1d {za7h.d[w15, 1]}, p7/z, [sp, x17, lsl #3] + +ld1q {za0h.q[w12, 0]}, p0/z, [x0] +ld1q {za0h.q[w12, 0]}, p0/z, [sp] +ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4] +ld1q {za0h.q[w12, 0]}, p0/z, [sp, x0, lsl #4] +ld1q {za15h.q[w15, 0]}, p7/z, [x17] +ld1q {za15h.q[w15, 0]}, p7/z, [sp] +ld1q {za15h.q[w15, 0]}, p7/z, [x0, x17, lsl #4] +ld1q {za15h.q[w15, 0]}, p7/z, [sp, x17, lsl #4] + +ld1b {za0v.b[w12, 0]}, p0/z, [x0] +ld1b {za0v.b[w12, 0]}, p0/z, [sp] +ld1b {za0v.b[w12, 0]}, p0/z, [sp, x0] +ld1b {za0v.b[w15, 15]}, p7/z, [x17] +ld1b {za0v.b[w15, 15]}, p7/z, [sp] +ld1b {za0v.b[w15, 15]}, p7/z, [sp, x17] + +ld1h {za0v.h[w12, 0]}, p0/z, [x0] +ld1h {za0v.h[w12, 0]}, p0/z, [sp] +ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1] +ld1h {za0v.h[w12, 0]}, p0/z, [sp, x0, lsl #1] +ld1h {za1v.h[w15, 7]}, p7/z, [x17] +ld1h {za1v.h[w15, 7]}, p7/z, [sp] +ld1h {za1v.h[w15, 7]}, p7/z, [x0, x17, lsl #1] +ld1h {za1v.h[w15, 7]}, p7/z, [sp, x17, lsl #1] + +ld1w {za0v.s[w12, 0]}, p0/z, [x0] +ld1w {za0v.s[w12, 0]}, p0/z, [sp] +ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2] +ld1w {za0v.s[w12, 0]}, p0/z, [sp, x0, lsl #2] +ld1w {za3v.s[w15, 3]}, p7/z, [x17] +ld1w {za3v.s[w15, 3]}, p7/z, [sp] +ld1w {za3v.s[w15, 3]}, p7/z, [x0, x17, lsl #2] +ld1w {za3v.s[w15, 3]}, p7/z, [sp, x17, lsl #2] + +ld1d {za0v.d[w12, 0]}, p0/z, [x0] +ld1d {za0v.d[w12, 0]}, p0/z, [sp] +ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3] +ld1d {za0v.d[w12, 0]}, p0/z, [sp, x0, lsl #3] +ld1d {za7v.d[w15, 1]}, p7/z, [x17] +ld1d {za7v.d[w15, 1]}, p7/z, [sp] +ld1d {za7v.d[w15, 1]}, p7/z, [x0, x17, lsl #3] +ld1d {za7v.d[w15, 1]}, p7/z, [sp, x17, lsl #3] + +ld1q {za0v.q[w12, 0]}, p0/z, [x0] +ld1q {za0v.q[w12, 0]}, p0/z, [sp] +ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4] +ld1q {za0v.q[w12, 0]}, p0/z, [sp, x0, lsl #4] +ld1q {za15v.q[w15, 0]}, p7/z, [x17] +ld1q {za15v.q[w15, 0]}, p7/z, [sp] +ld1q {za15v.q[w15, 0]}, p7/z, [x0, x17, lsl #4] +ld1q {za15v.q[w15, 0]}, p7/z, [sp, x17, lsl #4] + +/* Register aliases. */ +foo .req za0v +bar .req w15 + +ld1q {foo.q[w12, #0]}, p0/z, [sp, x0, lsl #4] +ld1q {za15v.q[bar, #0]}, p7/z, [x17] + +/* Optional LSL operator. */ +ld1b {za0v.b[w15, 15]}, p7/z, [sp, x0, lsl #0] +ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1] +ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1] +ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1] +ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1] +ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1] diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.d b/gas/testsuite/gas/aarch64/sme-6-illegal.d new file mode 100644 index 0000000..fd3f7f3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme-6-illegal.s +#error_output: sme-6-illegal.l diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l new file mode 100644 index 0000000..233c12a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -0,0 +1,45 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]' +[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]' +[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]' +[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' +[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.s b/gas/testsuite/gas/aarch64/sme-6-illegal.s new file mode 100644 index 0000000..d0de01d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.s @@ -0,0 +1,46 @@ +/* Scalable Matrix Extension (SME). */ + +st1b {za0h.b[w11, 0]}, p0, [x0] +st1h {za0h.h[w16, 0]}, p0, [x0] +st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #3] +st1w {za3v.s[w15, 3]}, p7, [sp, lsl #2] +st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #12] +st1q {za0v.q[w12]}, p0, [x0, x0, lsl #2] +st1b {za1h.b[w12, 0]}, p0, [x0] +st1b {za1v.b[w12, 0]}, p0, [sp] +st1b {za1h.b[w12, 0]}, p0, [sp, x0] +st1b {za0v.b[w15, 16]}, p7, [x17] +st1b {za0h.b[w15, 16]}, p7, [sp] +st1b {za0v.b[w15, 16]}, p7, [sp, x17] +st1h {za2v.h[w12, 0]}, p0, [x0] +st1h {za2h.h[w12, 0]}, p0, [sp] +st1h {za2v.h[w12, 0]}, p0, [x0, x0, lsl #1] +st1h {za2h.h[w12, 0]}, p0, [sp, x0, lsl #1] +st1h {za1v.h[w15, 8]}, p7, [x17] +st1h {za1h.h[w15, 8]}, p7, [sp] +st1h {za1v.h[w15, 8]}, p7, [x0, x17, lsl #1] +st1h {za1h.h[w15, 8]}, p7, [sp, x17, lsl #1] +st1w {za4h.s[w12, 0]}, p0, [x0] +st1w {za4v.s[w12, 0]}, p0, [sp] +st1w {za4h.s[w12, 0]}, p0, [x0, x0, lsl #2] +st1w {za4v.s[w12, 0]}, p0, [sp, x0, lsl #2] +st1w {za3h.s[w15, 4]}, p7, [x17] +st1w {za3v.s[w15, 4]}, p7, [sp] +st1w {za3h.s[w15, 4]}, p7, [x0, x17, lsl #2] +st1w {za3v.s[w15, 4]}, p7, [sp, x17, lsl #2] +st1d {za8v.d[w12, 0]}, p0, [x0] +st1d {za8h.d[w12, 0]}, p0, [sp] +st1d {za8v.d[w12, 0]}, p0, [x0, x0, lsl #3] +st1d {za8h.d[w12, 0]}, p0, [sp, x0, lsl #3] +st1d {za7v.d[w15, 2]}, p7, [x17] +st1d {za7h.d[w15, 2]}, p7, [sp] +st1d {za7v.d[w15, 2]}, p7, [x0, x17, lsl #3] +st1d {za7h.d[w15, 2]}, p7, [sp, x17, lsl #3] +st1q {za16v.q[w12]}, p0, [x0] +st1q {za16h.q[w12]}, p0, [sp] +st1q {za16v.q[w12]}, p0, [x0, x0, lsl #4] +st1q {za16h.q[w12]}, p0, [sp, x0, lsl #4] +st1q {za15v.q[w15, 1]}, p7, [x17] +st1q {za15h.q[w15, 1]}, p7, [sp] +st1q {za15v.q[w15, 1]}, p7, [x0, x17, lsl #4] +st1q {za15h.q[w15, 1]}, p7, [sp, x17, lsl #4] diff --git a/gas/testsuite/gas/aarch64/sme-6.d b/gas/testsuite/gas/aarch64/sme-6.d new file mode 100644 index 0000000..1b1d32a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-6.d @@ -0,0 +1,85 @@ +#name: SME extension (ST1x instructions) +#as: -march=armv8-a+sme +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: e03f0000 st1b {za0h.b\[w12, 0\]}, p0, \[x0, xzr\] + 4: e03f03e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, xzr\] + 8: e02003e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, x0\] + c: e03f7e2f st1b {za0h.b\[w15, 15\]}, p7, \[x17, xzr\] + 10: e03f7fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, xzr\] + 14: e0317fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, x17\] + 18: e07f0000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\] + 1c: e07f03e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\] + 20: e0600000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\] + 24: e06003e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\] + 28: e07f7e2f st1h {za1h.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\] + 2c: e07f7fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\] + 30: e0717c0f st1h {za1h.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\] + 34: e0717fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\] + 38: e0bf0000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\] + 3c: e0bf03e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\] + 40: e0a00000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\] + 44: e0a003e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\] + 48: e0bf7e2f st1w {za3h.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\] + 4c: e0bf7fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\] + 50: e0b17c0f st1w {za3h.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\] + 54: e0b17fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\] + 58: e0ff0000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\] + 5c: e0ff03e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\] + 60: e0e00000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\] + 64: e0e003e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\] + 68: e0ff7e2f st1d {za7h.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\] + 6c: e0ff7fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\] + 70: e0f17c0f st1d {za7h.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\] + 74: e0f17fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\] + 78: e1ff0000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\] + 7c: e1ff03e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\] + 80: e1e00000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\] + 84: e1e003e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\] + 88: e1ff7e2f st1q {za15h.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\] + 8c: e1ff7fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\] + 90: e1f17c0f st1q {za15h.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\] + 94: e1f17fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\] + 98: e03f8000 st1b {za0v.b\[w12, 0\]}, p0, \[x0, xzr\] + 9c: e03f83e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, xzr\] + a0: e02083e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, x0\] + a4: e03ffe2f st1b {za0v.b\[w15, 15\]}, p7, \[x17, xzr\] + a8: e03fffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, xzr\] + ac: e031ffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, x17\] + b0: e07f8000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\] + b4: e07f83e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\] + b8: e0608000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\] + bc: e06083e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\] + c0: e07ffe2f st1h {za1v.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\] + c4: e07fffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\] + c8: e071fc0f st1h {za1v.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\] + cc: e071ffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\] + d0: e0bf8000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\] + d4: e0bf83e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\] + d8: e0a08000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\] + dc: e0a083e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\] + e0: e0bffe2f st1w {za3v.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\] + e4: e0bfffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\] + e8: e0b1fc0f st1w {za3v.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\] + ec: e0b1ffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\] + f0: e0ff8000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\] + f4: e0ff83e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\] + f8: e0e08000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\] + fc: e0e083e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\] + 100: e0fffe2f st1d {za7v.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\] + 104: e0ffffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\] + 108: e0f1fc0f st1d {za7v.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\] + 10c: e0f1ffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\] + 110: e1ff8000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\] + 114: e1ff83e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\] + 118: e1e08000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\] + 11c: e1e083e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\] + 120: e1fffe2f st1q {za15v.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\] + 124: e1ffffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\] + 128: e1f1fc0f st1q {za15v.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\] + 12c: e1f1ffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sme-6.s b/gas/testsuite/gas/aarch64/sme-6.s new file mode 100644 index 0000000..143f02a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-6.s @@ -0,0 +1,86 @@ +/* SME Extension (ST1x instructions). */ +st1b {za0h.b[w12, 0]}, p0, [x0] +st1b {za0h.b[w12, 0]}, p0, [sp] +st1b {za0h.b[w12, 0]}, p0, [sp, x0] +st1b {za0h.b[w15, 15]}, p7, [x17] +st1b {za0h.b[w15, 15]}, p7, [sp] +st1b {za0h.b[w15, 15]}, p7, [sp, x17] + +st1h {za0h.h[w12, 0]}, p0, [x0] +st1h {za0h.h[w12, 0]}, p0, [sp] +st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1] +st1h {za0h.h[w12, 0]}, p0, [sp, x0, lsl #1] +st1h {za1h.h[w15, 7]}, p7, [x17] +st1h {za1h.h[w15, 7]}, p7, [sp] +st1h {za1h.h[w15, 7]}, p7, [x0, x17, lsl #1] +st1h {za1h.h[w15, 7]}, p7, [sp, x17, lsl #1] + +st1w {za0h.s[w12, 0]}, p0, [x0] +st1w {za0h.s[w12, 0]}, p0, [sp] +st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2] +st1w {za0h.s[w12, 0]}, p0, [sp, x0, lsl #2] +st1w {za3h.s[w15, 3]}, p7, [x17] +st1w {za3h.s[w15, 3]}, p7, [sp] +st1w {za3h.s[w15, 3]}, p7, [x0, x17, lsl #2] +st1w {za3h.s[w15, 3]}, p7, [sp, x17, lsl #2] + +st1d {za0h.d[w12, 0]}, p0, [x0] +st1d {za0h.d[w12, 0]}, p0, [sp] +st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3] +st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #3] +st1d {za7h.d[w15, 1]}, p7, [x17] +st1d {za7h.d[w15, 1]}, p7, [sp] +st1d {za7h.d[w15, 1]}, p7, [x0, x17, lsl #3] +st1d {za7h.d[w15, 1]}, p7, [sp, x17, lsl #3] + +st1q {za0h.q[w12, 0]}, p0, [x0] +st1q {za0h.q[w12, 0]}, p0, [sp] +st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4] +st1q {za0h.q[w12, 0]}, p0, [sp, x0, lsl #4] +st1q {za15h.q[w15, 0]}, p7, [x17] +st1q {za15h.q[w15, 0]}, p7, [sp] +st1q {za15h.q[w15, 0]}, p7, [x0, x17, lsl #4] +st1q {za15h.q[w15, 0]}, p7, [sp, x17, lsl #4] + +st1b {za0v.b[w12, 0]}, p0, [x0] +st1b {za0v.b[w12, 0]}, p0, [sp] +st1b {za0v.b[w12, 0]}, p0, [sp, x0] +st1b {za0v.b[w15, 15]}, p7, [x17] +st1b {za0v.b[w15, 15]}, p7, [sp] +st1b {za0v.b[w15, 15]}, p7, [sp, x17] + +st1h {za0v.h[w12, 0]}, p0, [x0] +st1h {za0v.h[w12, 0]}, p0, [sp] +st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1] +st1h {za0v.h[w12, 0]}, p0, [sp, x0, lsl #1] +st1h {za1v.h[w15, 7]}, p7, [x17] +st1h {za1v.h[w15, 7]}, p7, [sp] +st1h {za1v.h[w15, 7]}, p7, [x0, x17, lsl #1] +st1h {za1v.h[w15, 7]}, p7, [sp, x17, lsl #1] + +st1w {za0v.s[w12, 0]}, p0, [x0] +st1w {za0v.s[w12, 0]}, p0, [sp] +st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2] +st1w {za0v.s[w12, 0]}, p0, [sp, x0, lsl #2] +st1w {za3v.s[w15, 3]}, p7, [x17] +st1w {za3v.s[w15, 3]}, p7, [sp] +st1w {za3v.s[w15, 3]}, p7, [x0, x17, lsl #2] +st1w {za3v.s[w15, 3]}, p7, [sp, x17, lsl #2] + +st1d {za0v.d[w12, 0]}, p0, [x0] +st1d {za0v.d[w12, 0]}, p0, [sp] +st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3] +st1d {za0v.d[w12, 0]}, p0, [sp, x0, lsl #3] +st1d {za7v.d[w15, 1]}, p7, [x17] +st1d {za7v.d[w15, 1]}, p7, [sp] +st1d {za7v.d[w15, 1]}, p7, [x0, x17, lsl #3] +st1d {za7v.d[w15, 1]}, p7, [sp, x17, lsl #3] + +st1q {za0v.q[w12, 0]}, p0, [x0] +st1q {za0v.q[w12, 0]}, p0, [sp] +st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4] +st1q {za0v.q[w12, 0]}, p0, [sp, x0, lsl #4] +st1q {za15v.q[w15, 0]}, p7, [x17] +st1q {za15v.q[w15, 0]}, p7, [sp] +st1q {za15v.q[w15, 0]}, p7, [x0, x17, lsl #4] +st1q {za15v.q[w15, 0]}, p7, [sp, x17, lsl #4] diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.d b/gas/testsuite/gas/aarch64/sme-7-illegal.d new file mode 100644 index 0000000..d9ca586 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme-7-illegal.s +#error_output: sme-7-illegal.l diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l new file mode 100644 index 0000000..913bd0e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l @@ -0,0 +1,33 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]' +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]' +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]' +[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]' +[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]' +[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w15,15\],\[sp,#15,mul#4\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,13\],\[x17,#23,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,13\],\[x17,#23,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]' +[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]' diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s new file mode 100644 index 0000000..0d92d84 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s @@ -0,0 +1,39 @@ +/* Scalable Matrix Extension (SME). */ + +/* Load vector to ZA array. */ +ldr za[w11, 0], [x0] +ldr za[w12, 1], [sp, x0] +ldr za[w12, 0], [sp, #1, mul vl] +ldr za[w13, 9], [x17, #19, mul vl] +ldr za[w13, 21], [x17, #21, mul vl] +ldr za[w15, 32], [x17, #15, mul vl] +ldr za[w16, 15], [sp, #15, mul vl] +ldr za[w12, 0], [x0, #0, mul #1] +ldr za[w13, 0], [sp, #0, mul #2] +ldr za[w14, 9], [x17, #9, mul #3] +ldr za[w15, 15], [sp, #15, mul #4] + +/* Store vector from ZA array. */ +str za[w11, 0], [x0] +str za[w12, 1], [sp, x0] +str za[w12, 0], [sp, #1, mul vl] +str za[w13, 9], [x17, #19, mul vl] +str za[w13, 21], [x17, #21, mul vl] +str za[w15, 32], [x17, #15, mul vl] +str za[w16, 15], [sp, #15, mul vl] +str za[w12, 0], [x0, #0, mul #1] +str za[w13, 0], [sp, #0, mul #2] +str za[w14, 9], [x17, #9, mul #3] +str za[w15, 15], [sp, #15, mul #4] + +/* Operands indexes are tied. */ +ldr za[w13, 13], [x17, #23, mul vl] +str za[w13, 13], [x17, #23, mul vl] +ldr za[w13, 23], [x17, #13, mul vl] +str za[w13, 23], [x17, #13, mul vl] +ldr za[w13, 16], [x17, #16, mul vl] +str za[w13, 16], [x17, #16, mul vl] +ldr za[w13, -1], [x17, #1, mul vl] +str za[w13, -1], [x17, #1, mul vl] +ldr za[w13, 1], [x17, #-1, mul vl] +str za[w13, 1], [x17, #-1, mul vl] diff --git a/gas/testsuite/gas/aarch64/sme-7.d b/gas/testsuite/gas/aarch64/sme-7.d new file mode 100644 index 0000000..19a3e61 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-7.d @@ -0,0 +1,27 @@ +#name: SME extension (LDR and STR instructions) +#as: -march=armv8-a+sme +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: e1000000 ldr za\[w12, 0\], \[x0\] + 4: e10003e0 ldr za\[w12, 0\], \[sp\] + 8: e1000000 ldr za\[w12, 0\], \[x0\] + c: e10003e0 ldr za\[w12, 0\], \[sp\] + 10: e1006220 ldr za\[w15, 0\], \[x17\] + 14: e1002229 ldr za\[w13, 9\], \[x17, #9, mul vl\] + 18: e100622f ldr za\[w15, 15\], \[x17, #15, mul vl\] + 1c: e10063ef ldr za\[w15, 15\], \[sp, #15, mul vl\] + 20: e1200000 str za\[w12, 0\], \[x0\] + 24: e12003e0 str za\[w12, 0\], \[sp\] + 28: e1200000 str za\[w12, 0\], \[x0\] + 2c: e12003e0 str za\[w12, 0\], \[sp\] + 30: e1206220 str za\[w15, 0\], \[x17\] + 34: e1202229 str za\[w13, 9\], \[x17, #9, mul vl\] + 38: e120622f str za\[w15, 15\], \[x17, #15, mul vl\] + 3c: e12063ef str za\[w15, 15\], \[sp, #15, mul vl\] + 40: e10003e0 ldr za\[w12, 0\], \[sp\] + 44: e1206220 str za\[w15, 0\], \[x17\] diff --git a/gas/testsuite/gas/aarch64/sme-7.s b/gas/testsuite/gas/aarch64/sme-7.s new file mode 100644 index 0000000..7582d6c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-7.s @@ -0,0 +1,27 @@ +/* SME Extension (LDR and STR instructions). */ +/* Load vector to ZA array. */ +ldr za[w12, 0], [x0] +ldr za[w12, 0], [sp] +ldr za[w12, 0], [x0, #0, mul vl] +ldr za[w12, 0], [sp, #0, mul vl] +ldr za[w15, 0], [x17] +ldr za[w13, 9], [x17, #9, mul vl] +ldr za[w15, 15], [x17, #15, mul vl] +ldr za[w15, 15], [sp, #15, mul vl] + +/* Store vector from ZA array. */ +str za[w12, 0], [x0] +str za[w12, 0], [sp] +str za[w12, 0], [x0, #0, mul vl] +str za[w12, 0], [sp, #0, mul vl] +str za[w15, 0], [x17] +str za[w13, 9], [x17, #9, mul vl] +str za[w15, 15], [x17, #15, mul vl] +str za[w15, 15], [sp, #15, mul vl] + +/* Register aliases. */ +foo .req w12 +bar .req w15 + +ldr za[foo, 0], [sp, #0, mul vl] +str za[bar, 0], [x17] |