Various fixes for the Z80 support.

	PR 25537
ld	* emultempl/z80.em: Remove machine compatability checking.

	PR 25517
	* testsuite/ld-z80/arch_ez80_adl.d: Update command line.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80n.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z180.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80n.d: Likewise.

bfd
	* cpu-z80.c: Add machine type compatibility checking.

gas
	* config/tc-z80.c (md_parse_option): Do not use an underscore
	prefix for local labels in SDCC compatability mode.
	(z80_start_line_hook): Remove SDCC dollar label support.
	* testsuite/gas/z80/sdcc.d: Update expected disassembly.
	* testsuite/gas/z80/sdcc.s: Likewise.

	* config/tc-z80.c: Add -march option.
	* doc/as.texi: Update Z80 documentation.
	* doc/c-z80.texi: Likewise.
	* testsuite/gas/z80/ez80_adl_all.d: Update command line.
	* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
	* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
	* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
	* testsuite/gas/z80/gbz80_all.d: Likewise.
	* testsuite/gas/z80/r800_extra.d: Likewise.
	* testsuite/gas/z80/r800_ii8.d: Likewise.
	* testsuite/gas/z80/r800_z80_doc.d: Likewise.
	* testsuite/gas/z80/sdcc.d: Likewise.
	* testsuite/gas/z80/z180.d: Likewise.
	* testsuite/gas/z80/z180_z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_ii8.d: Likewise.
	* testsuite/gas/z80/z80_in_f_c.d: Likewise.
	* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
	* testsuite/gas/z80/z80_out_c_0.d: Likewise.
	* testsuite/gas/z80/z80_sli.d: Likewise.
	* testsuite/gas/z80/z80n_all.d: Likewise.
	* testsuite/gas/z80/z80n_reloc.d: Likewise.

25 files changed, 209 insertions, 229 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5626274..e722633 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,39 @@
+2020-02-19  Sergey Belyashov  <sergey.belyashov@gmail.com>
+
+	PR 25576
+	* config/tc-z80.c (md_parse_option): Do not use an underscore
+	prefix for local labels in SDCC compatability mode.
+	(z80_start_line_hook): Remove SDCC dollar label support.
+	* testsuite/gas/z80/sdcc.d: Update expected disassembly.
+	* testsuite/gas/z80/sdcc.s: Likewise.
+
+2020-02-19  Sergey Belyashov  <sergey.belyashov@gmail.com>
+
+	PR 25517
+	* config/tc-z80.c: Add -march option.
+	* doc/as.texi: Update Z80 documentation.
+	* doc/c-z80.texi: Likewise.
+	* testsuite/gas/z80/ez80_adl_all.d: Update command line.
+	* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
+	* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
+	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
+	* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
+	* testsuite/gas/z80/gbz80_all.d: Likewise.
+	* testsuite/gas/z80/r800_extra.d: Likewise.
+	* testsuite/gas/z80/r800_ii8.d: Likewise.
+	* testsuite/gas/z80/r800_z80_doc.d: Likewise.
+	* testsuite/gas/z80/sdcc.d: Likewise.
+	* testsuite/gas/z80/z180.d: Likewise.
+	* testsuite/gas/z80/z180_z80_doc.d: Likewise.
+	* testsuite/gas/z80/z80_doc.d: Likewise.
+	* testsuite/gas/z80/z80_ii8.d: Likewise.
+	* testsuite/gas/z80/z80_in_f_c.d: Likewise.
+	* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
+	* testsuite/gas/z80/z80_out_c_0.d: Likewise.
+	* testsuite/gas/z80/z80_sli.d: Likewise.
+	* testsuite/gas/z80/z80n_all.d: Likewise.
+	* testsuite/gas/z80/z80n_reloc.d: Likewise.
+
 2020-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
index abe8c11..0ed43cb 100644
--- a/gas/config/tc-z80.c
+++ b/gas/config/tc-z80.c
@@ -38,13 +38,12 @@ const char * md_shortopts = ""; /* None yet.  */
 
 enum options
 {
-  OPTION_MACH_Z80 = OPTION_MD_BASE,
+  OPTION_MARCH = OPTION_MD_BASE,
+  OPTION_MACH_Z80,
   OPTION_MACH_R800,
   OPTION_MACH_Z180,
   OPTION_MACH_EZ80_Z80,
   OPTION_MACH_EZ80_ADL,
-  OPTION_MACH_GBZ80,
-  OPTION_MACH_Z80N,
   OPTION_MACH_INST,
   OPTION_MACH_NO_INST,
   OPTION_MACH_IUD,
@@ -83,13 +82,12 @@ enum options
 
 struct option md_longopts[] =
 {
+  { "march",     required_argument, NULL, OPTION_MARCH},
   { "z80",       no_argument, NULL, OPTION_MACH_Z80},
   { "r800",      no_argument, NULL, OPTION_MACH_R800},
   { "z180",      no_argument, NULL, OPTION_MACH_Z180},
   { "ez80",      no_argument, NULL, OPTION_MACH_EZ80_Z80},
   { "ez80-adl",  no_argument, NULL, OPTION_MACH_EZ80_ADL},
-  { "gbz80",     no_argument, NULL, OPTION_MACH_GBZ80},
-  { "z80n",      no_argument, NULL, OPTION_MACH_Z80N},
   { "fp-s",      required_argument, NULL, OPTION_FP_SINGLE_FORMAT},
   { "fp-d",      required_argument, NULL, OPTION_FP_DOUBLE_FORMAT},
   { "strict",    no_argument, NULL, OPTION_MACH_FUD},
@@ -145,6 +143,83 @@ static str_to_float_t str_to_double;
 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
 static char inst_mode;
 
+struct match_info
+{
+  const char *name;
+  int ins_ok;
+  int ins_err;
+  int cpu_mode;
+  const char *comment;
+};
+
+static const struct match_info
+match_cpu_table [] =
+{
+  {"z80",     INS_Z80, 0, 0, "Zilog Z80 (+infc+xyhl)" },
+  {"ez80",    INS_EZ80, 0, 0, "Zilog eZ80" },
+  {"gbz80",   INS_GBZ80, INS_UNDOC|INS_UNPORT, 0, "GameBoy Z80" },
+  {"r800",    INS_R800, INS_UNPORT, 0, "Ascii R800" },
+  {"z180",    INS_Z180, INS_UNDOC|INS_UNPORT, 0, "Zilog Z180" },
+  {"z80n",    INS_Z80N, 0, 0, "Z80 Next" }
+};
+
+static const struct match_info
+match_ext_table [] =
+{
+  {"full",    INS_UNDOC|INS_UNPORT, 0, 0, "assemble all known instructions" },
+  {"adl",     0, 0, 1, "eZ80 ADL mode by default" },
+  {"xyhl",    INS_IDX_HALF, 0, 0, "instructions with halves of index registers" },
+  {"infc",    INS_IN_F_C, 0, 0, "instruction IN F,(C)" },
+  {"outc0",   INS_OUT_C_0, 0, 0, "instruction OUT (C),0" },
+  {"sli",     INS_SLI, 0, 0, "instruction known as SLI, SLL, or SL1" },
+  {"xdcb",    INS_ROT_II_LD, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" }
+};
+
+static void
+setup_march (const char *name, int *ok, int *err, int *mode)
+{
+  unsigned i;
+  size_t len = strcspn (name, "+-");
+  for (i = 0; i < ARRAY_SIZE (match_cpu_table); ++i)
+    if (!strncasecmp (name, match_cpu_table[i].name, len)
+	&& strlen (match_cpu_table[i].name) == len)
+      {
+	*ok = match_cpu_table[i].ins_ok;
+	*err = match_cpu_table[i].ins_err;
+	*mode = match_cpu_table[i].cpu_mode;
+	break;
+      }
+
+  if (i >= ARRAY_SIZE (match_cpu_table))
+    as_fatal (_("Invalid CPU is specified: %s"), name);
+
+  while (name[len])
+    {
+      name = &name[len + 1];
+      len = strcspn (name, "+-");
+      for (i = 0; i < ARRAY_SIZE (match_ext_table); ++i)
+	if (!strncasecmp (name, match_ext_table[i].name, len)
+	    && strlen (match_ext_table[i].name) == len)
+	  {
+	    if (name[-1] == '+')
+	      {
+		*ok |= match_ext_table[i].ins_ok;
+		*err &= ~match_ext_table[i].ins_ok;
+		*mode |= match_ext_table[i].cpu_mode;
+	      }
+	    else
+	      {
+		*ok &= ~match_ext_table[i].ins_ok;
+		*err |= match_ext_table[i].ins_ok;
+		*mode &= ~match_ext_table[i].cpu_mode;
+	      }
+	    break;
+	  }
+      if (i >= ARRAY_SIZE (match_ext_table))
+	as_fatal (_("Invalid EXTENTION is specified: %s"), name);
+    }
+}
+
 static int
 setup_instruction (const char *inst, int *add, int *sub)
 {
@@ -243,35 +318,23 @@ md_parse_option (int c, const char* arg)
     {
     default:
       return 0;
+    case OPTION_MARCH:
+      setup_march (arg, & ins_ok, & ins_err, & cpu_mode);
+      break;
     case OPTION_MACH_Z80:
-      ins_ok = (ins_ok & INS_TUNE_MASK) | INS_Z80;
-      ins_err = (ins_err & INS_MARCH_MASK) | (~INS_Z80 & INS_MARCH_MASK);
+      setup_march ("z80", & ins_ok, & ins_err, & cpu_mode);
       break;
     case OPTION_MACH_R800:
-      ins_ok = INS_R800 | INS_IDX_HALF | INS_IN_F_C;
-      ins_err = INS_UNPORT;
+      setup_march ("r800", & ins_ok, & ins_err, & cpu_mode);
       break;
     case OPTION_MACH_Z180:
-      ins_ok = INS_Z180;
-      ins_err = INS_UNDOC | INS_UNPORT;
+      setup_march ("z180", & ins_ok, & ins_err, & cpu_mode);
       break;
     case OPTION_MACH_EZ80_Z80:
-      ins_ok = INS_EZ80 | INS_IDX_HALF;
-      ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
-      cpu_mode = 0;
+      setup_march ("ez80", & ins_ok, & ins_err, & cpu_mode);
       break;
     case OPTION_MACH_EZ80_ADL:
-      ins_ok = INS_EZ80 | INS_IDX_HALF;
-      ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
-      cpu_mode = 1;
-      break;
-    case OPTION_MACH_GBZ80:
-      ins_ok = INS_GBZ80;
-      ins_err = INS_UNDOC | INS_UNPORT;
-      break;
-    case OPTION_MACH_Z80N:
-      ins_ok = INS_Z80N | INS_UNPORT | INS_UNDOC;
-      ins_err = 0;
+      setup_march ("ez80+adl", & ins_ok, & ins_err, & cpu_mode);
       break;
     case OPTION_FP_SINGLE_FORMAT:
       str_to_float = get_str_to_float (arg);
@@ -319,7 +382,6 @@ md_parse_option (int c, const char* arg)
       break;
     case OPTION_COMPAT_SDCC:
       sdcc_compat = 1;
-      local_label_prefix = "_";
       break;
     case OPTION_COMPAT_COLONLESS:
       colonless_labels = 1;
@@ -332,16 +394,17 @@ md_parse_option (int c, const char* arg)
 void
 md_show_usage (FILE * f)
 {
-  fprintf (f, "\n\
+  unsigned i;
+  fprintf (f, _("\n\
 CPU model options:\n\
-  -z80\t\t\t  assemble for Zilog Z80\n\
-  -r800\t\t\t  assemble for Ascii R800\n\
-  -z180\t\t\t  assemble for Zilog Z180\n\
-  -ez80\t\t\t  assemble for Zilog eZ80 in Z80 mode by default\n\
-  -ez80-adl\t\t  assemble for Zilog eZ80 in ADL mode by default\n\
-  -gbz80\t\t  assemble for GameBoy Z80\n\
-  -z80n\t\t\t  assemble for Z80N\n\
-\n\
+  -march=CPU[+EXT...][-EXT...]\n\
+\t\t\t  generate code for CPU, where CPU is one of:\n"));
+  for (i = 0; i < ARRAY_SIZE(match_cpu_table); ++i)
+    fprintf (f, "  %-8s\t\t  %s\n", match_cpu_table[i].name, match_cpu_table[i].comment);
+  fprintf (f, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n"));
+  for (i = 0; i < ARRAY_SIZE(match_ext_table); ++i)
+    fprintf (f, "  %-8s\t\t  %s\n", match_ext_table[i].name, match_ext_table[i].comment);
+  fprintf (f, _("\n\
 Compatibility options:\n\
   -local-prefix=TEXT\t  treat labels prefixed by TEXT as local\n\
   -colonless\t\t  permit colonless labels\n\
@@ -349,42 +412,14 @@ Compatibility options:\n\
   -fp-s=FORMAT\t\t  set single precission FP numbers format\n\
   -fp-d=FORMAT\t\t  set double precission FP numbers format\n\
 Where FORMAT one of:\n\
-  ieee754\t\t  IEEE754 compatible\n\
+  ieee754\t\t  IEEE754 compatible (depends on directive)\n\
   half\t\t\t  IEEE754 half precision (16 bit)\n\
   single\t\t  IEEE754 single precision (32 bit)\n\
   double\t\t  IEEE754 double precision (64 bit)\n\
   zeda32\t\t  Zeda z80float library 32 bit format\n\
   math48\t\t  48 bit format from Math48 library\n\
 \n\
-Support for known undocumented instructions:\n\
-  -strict\t\t  assemble only documented instructions\n\
-  -full\t\t\t  assemble all undocumented instructions\n\
-  -with-inst=INST[,...]\n\
-  -Wnins INST[,...]\t  assemble specified instruction(s)\n\
-  -without-inst=INST[,...]\n\
-  -Fins INST[,...]\t  do not assemble specified instruction(s)\n\
-Where INST is one of:\n\
-  idx-reg-halves\t  instructions with halves of index registers\n\
-  sli\t\t\t  instruction SLI/SLL\n\
-  op-ii-ld\t\t  instructions like SLA (II+dd),R (opcodes DD/FD CB dd xx)\n\
-  in-f-c\t\t  instruction IN F,(C)\n\
-  out-c-0\t\t  instruction OUT (C),0\n\
-\n\
-Obsolete options:\n\
-  -ignore-undocumented-instructions\n\
-  -Wnud\t\t\t  silently assemble undocumented Z80-instructions that work on R800\n\
-  -ignore-unportable-instructions\n\
-  -Wnup\t\t\t  silently assemble all undocumented Z80-instructions\n\
-  -warn-undocumented-instructions\n\
-  -Wud\t\t\t  issue warnings for undocumented Z80-instructions that work on R800\n\
-  -warn-unportable-instructions\n\
-  -Wup\t\t\t  issue warnings for other undocumented Z80-instructions\n\
-  -forbid-undocumented-instructions\n\
-  -Fud\t\t\t  treat all undocumented Z80-instructions as errors\n\
-  -forbid-unportable-instructions\n\
-  -Fup\t\t\t  treat undocumented Z80-instructions that do not work on R800 as errors\n\
-\n\
-Default: -z80 -ignore-undocumented-instructions -warn-unportable-instructions.\n");
+Default: -march=z80+xyhl+infc\n"));
 }
 
 static symbolS * zero;
@@ -499,12 +534,7 @@ z80_md_end (void)
   switch (ins_ok & INS_MARCH_MASK)
     {
     case INS_Z80:
-      if (ins_ok & INS_UNPORT)
-        mach_type = bfd_mach_z80full;
-      else if (ins_ok & INS_UNDOC)
-        mach_type = bfd_mach_z80;
-      else
-        mach_type = bfd_mach_z80strict;
+      mach_type = bfd_mach_z80;
       break;
     case INS_R800:
       mach_type = bfd_mach_r800;
@@ -524,40 +554,17 @@ z80_md_end (void)
     default:
       mach_type = 0;
     }
-
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_type);
 }
 
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
 void
 z80_elf_final_processing (void)
-{
+{/* nothing to do, all is done by BFD itself */
+/*
   unsigned elf_flags;
-  switch (ins_ok & INS_MARCH_MASK)
-    {
-    case INS_Z80:
-      elf_flags = EF_Z80_MACH_Z80;
-      break;
-    case INS_R800:
-      elf_flags = EF_Z80_MACH_R800;
-      break;
-    case INS_Z180:
-      elf_flags = EF_Z80_MACH_Z180;
-      break;
-    case INS_GBZ80:
-      elf_flags = EF_Z80_MACH_GBZ80;
-      break;
-    case INS_EZ80:
-      elf_flags = cpu_mode ? EF_Z80_MACH_EZ80_ADL : EF_Z80_MACH_EZ80_Z80;
-      break;
-    case INS_Z80N:
-      elf_flags = EF_Z80_MACH_Z80N;
-      break;
-    default:
-      elf_flags = 0;
-    }
-
   elf_elfheader (stdoutput)->e_flags = elf_flags;
+*/
 }
 #endif
 
@@ -631,8 +638,6 @@ z80_start_line_hook (void)
             }
           c = ':';
         }
-      if (c == ':' && sdcc_compat && rest[-2] != '$')
-        dollar_label_clear ();
       if (*rest == ':')
         {
           /* remove second colon if SDCC compatibility enabled */
@@ -1222,7 +1227,7 @@ emit_mx (char prefix, char opcode, int shift, expressionS * arg)
 	  if ((prefix == 0) && (rnum & R_INDEX))
 	    {
 	      prefix = (rnum & R_IX) ? 0xDD : 0xFD;
-              if (!(ins_ok & INS_EZ80))
+	      if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
                 check_mach (INS_IDX_HALF);
 	      rnum &= ~R_INDEX;
 	    }
@@ -1312,7 +1317,8 @@ emit_mr (char prefix, char opcode, const char *args)
 	      ill_op ();
 	      break;
 	    }
-	  check_mach (INS_ROT_II_LD);
+	  if (!(ins_ok & INS_Z80N))
+	    check_mach (INS_ROT_II_LD);
 	}
       /* Fall through.  */
     case O_register:
@@ -1926,7 +1932,7 @@ emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
 	    {
               if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80))
                 ill_op ();
-              else if (reg.X_add_number == REG_F && !(ins_ok & INS_R800))
+	      else if (reg.X_add_number == REG_F && !(ins_ok & (INS_R800|INS_Z80N)))
                 check_mach (INS_IN_F_C);
           q = frag_more (2);
           *q++ = 0xED;
@@ -1994,7 +2000,8 @@ emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
   /* Allow "out (c), 0" as unportable instruction.  */
   if (reg.X_op == O_constant && reg.X_add_number == 0)
     {
-      check_mach (INS_OUT_C_0);
+      if (!(ins_ok & INS_Z80N))
+	check_mach (INS_OUT_C_0);
       reg.X_op = O_register;
       reg.X_add_number = 6;
     }
@@ -2368,7 +2375,7 @@ emit_ld_r_n (expressionS *dst, expressionS *src)
     {
       if (ins_ok & INS_GBZ80)
         ill_op ();
-      else if (!(ins_ok & INS_EZ80))
+      else if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
         check_mach (INS_IDX_HALF);
       *q++ = prefix;
     }
@@ -2529,7 +2536,7 @@ emit_ld_r_r (expressionS *dst, expressionS *src)
     }
   if ((ins_ok & INS_GBZ80) && prefix != 0)
     ill_op ();
-  if (ii_halves && !(ins_ok & INS_EZ80))
+  if (ii_halves && !(ins_ok & (INS_EZ80|INS_R800|INS_Z80N)))
     check_mach (INS_IDX_HALF);
   if (prefix == 0 && (ins_ok & INS_EZ80))
     {
@@ -3545,10 +3552,10 @@ static table_t instab[] =
   { "scf",  0x00, 0x37, emit_insn, INS_ALL },
   { "set",  0xCB, 0xC0, emit_bit,  INS_ALL },
   { "setae",0xED, 0x95, emit_insn, INS_Z80N },
-  { "sl1",  0xCB, 0x30, emit_mr,   INS_SLI },
+  { "sl1",  0xCB, 0x30, emit_mr,   INS_SLI|INS_Z80N },
   { "sla",  0xCB, 0x20, emit_mr,   INS_ALL },
-  { "sli",  0xCB, 0x30, emit_mr,   INS_SLI },
-  { "sll",  0xCB, 0x30, emit_mr,   INS_SLI },
+  { "sli",  0xCB, 0x30, emit_mr,   INS_SLI|INS_Z80N },
+  { "sll",  0xCB, 0x30, emit_mr,   INS_SLI|INS_Z80N },
   { "slp",  0xED, 0x76, emit_insn, INS_Z180|INS_EZ80 },
   { "sra",  0xCB, 0x28, emit_mr,   INS_ALL },
   { "srl",  0xCB, 0x38, emit_mr,   INS_ALL },
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 1554c51..e97042c 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -630,21 +630,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @ifset Z80
 
 @emph{Target Z80 options:}
-  [@b{-z80}]|[@b{-z180}]|[@b{-r800}]|[@b{-ez80}]|[@b{-ez80-adl}]
+  [@b{-march=@var{CPU}@var{[-EXT]}@var{[+EXT]}}]
   [@b{-local-prefix=}@var{PREFIX}]
   [@b{-colonless}]
   [@b{-sdcc}]
   [@b{-fp-s=}@var{FORMAT}]
   [@b{-fp-d=}@var{FORMAT}]
-  [@b{-strict}]|[@b{-full}]
-  [@b{-with-inst=@var{INST}[,...]}] [@b{-Wnins @var{INST}[,...]}]
-  [@b{-without-inst=@var{INST}[,...]}] [@b{-Fins @var{INST}[,...]}]
-  [@b{ -ignore-undocumented-instructions}] [@b{-Wnud}]
-  [@b{ -ignore-unportable-instructions}] [@b{-Wnup}]
-  [@b{ -warn-undocumented-instructions}] [@b{-Wud}]
-  [@b{ -warn-unportable-instructions}] [@b{-Wup}]
-  [@b{ -forbid-undocumented-instructions}] [@b{-Fud}]
-  [@b{ -forbid-unportable-instructions}] [@b{-Fup}]
 @end ifset
 @ifset Z8000
 
diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
index e768e38..d2dbac1 100644
--- a/gas/doc/c-z80.texi
+++ b/gas/doc/c-z80.texi
@@ -29,37 +29,35 @@
 @cindex options for Z80
 @c man begin OPTIONS
 @table @gcctabopt
-@cindex @code{-z80} command-line option, Z80
-@item -z80
-Produce code for the Zilog Z80 processor. By default accepted undocumented
-operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL},
-@code{IYH}) and instuction @code{IN F,(C)}. Other useful undocumented
-instructions produces warnings. Undocumented instructions may not work on some
-CPUs, use them on your own risk.
-
-@cindex @code{-r800} command-line option, Z80
-@item -r800
-Produce code for the Ascii R800 processor.
-
-@cindex @code{-z180} command-line option, Z80
-@item -z180
-Produce code for the Zilog Z180 processor.
-
-@cindex @code{-ez80} command-line option, Z80
-@item -ez80
-Produce code for the eZ80 processor in Z80 memory mode by default.
-
-@cindex @code{-ez80-adl} command-line option, Z80
-@item -ez80-adl
-Produce code for the eZ80 processor in ADL memory mode by default.
-
-@cindex @code{-gbz80} command-line option, Z80
-@item -gbz80
-Produce code for the GameBoy Z80 processor.
-
-@cindex @code{-z80n} command-line option, Z80
-@item -z80n
-Produce code for the Z80N processor.
+
+@cindex @samp{-march=} option, Z80
+@item -march=@var{CPU}[-@var{EXT}@dots{}][+@var{EXT}@dots{}]
+This option specifies the target processor. The assembler will issue
+an error message if an attempt is made to assemble an instruction which
+will not execute on the target processor. The following processor names
+are recognized:
+@code{z80},
+@code{z180},
+@code{ez80},
+@code{gbz80},
+@code{z80n},
+@code{r800}.
+In addition to the basic instruction set, the assembler can be told to
+accept some extention mnemonics. For example,
+@code{-march=z180+sli+infc} extends @var{z180} with @var{SLI} instructions and
+@var{IN F,(C)}. The following instructions are currently supported:
+@code{full} (all known instructions),
+@code{adl} (ADL CPU mode by default),
+@code{sli} (instruction known as @var{SLI}, @var{SLL} or @var{SL1}),
+@code{xyhl} (instructions with halves of index registers: @var{IXL}, @var{IXH},
+@var{IYL}, @var{IYH}),
+@code{xdcb} (instructions like @var{RotOp (II+d),R} and @var{BitOp n,(II+d),R}),
+@code{infc} (instruction @var{IN F,(C)} or @var{IN (C)}),
+@code{outc0} (instruction @var{OUT (C),0}).
+Note that rather than extending a basic instruction set, the extention
+mnemonics starting with @code{-} revoke the respective functionality:
+@code{-march=z80-full+xyhl} first removes all default extentions and adds
+support for index registers halves only.
 
 @cindex @code{-local-prefix} command-line option, Z80
 @item  -local-prefix=@var{prefix}
@@ -82,44 +80,6 @@ Single precision floating point numbers format. Default: ieee754 (32 bit).
 @cindex @code{-fp-d} command-line option, Z80
 @item -fp-d=@var{FORMAT}
 Double precision floating point numbers format. Default: ieee754 (64 bit).
-
-@cindex @code{-strict} command-line option, Z80
-@item  -strict
-Accept documented instructions only.
-
-@cindex @code{-full} command-line option, Z80
-@item  -full
-Accept all known Z80 instructions.
-
-@item  -with-inst=@var{INST}[,...]
-@itemx -Wnins @var{INST}[,...]
-Enable specified undocumented instruction(s).
-
-@item  -without-inst=@var{INST}[,...]
-@itemx -Fins @var{INST}[,...]
-Disable specified undocumented instruction(s).
-
-@item  -ignore-undocumented-instructions
-@itemx -Wnud
-Silently assemble undocumented Z80-instructions that have been adopted
-as documented R800-instructions .
-@item  -ignore-unportable-instructions
-@itemx -Wnup
-Silently assemble all undocumented Z80-instructions.
-@item  -warn-undocumented-instructions
-@itemx -Wud
-Issue warnings for undocumented Z80-instructions that work on R800, do
-not assemble other undocumented instructions without warning.
-@item  -warn-unportable-instructions
-@itemx -Wup
-Issue warnings for other undocumented Z80-instructions, do not treat any
-undocumented instructions as errors.
-@item  -forbid-undocumented-instructions
-@itemx -Fud
-Treat all undocumented z80-instructions as errors.
-@item  -forbid-unportable-instructions
-@itemx -Fup
-Treat undocumented z80-instructions that do not work on R800 as errors.
 @end table
 @c man end
 
@@ -144,21 +104,6 @@ Double precision IEEE754 compatible format (64 bits).
 48 bit floating point format from Math48 package by Anders Hejlsberg.
 @end table
 
-Known undocumented instructions.
-@table @option
-@cindex Known undocumented instructions
-@item  @code{idx-reg-halves}
-All operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL}, @code{IYH}).
-@item  @code{sli}
-@code{SLI} or @code{SLL} instruction. Same as @code{SLA r; INC r}.
-@item  @code{op-ii-ld}
-Istructions like @code{<op> (<ii>+<d>),<r>}. For example: @code{RL (IX+5),C}
-@item @code{in-f-c}
-Instruction @code{IN F,(C)}.
-@item @code{out-c-0}
-Instruction @code{OUT (C),0}
-@end table
-
 @cindex Z80 Syntax
 @node Z80 Syntax
 @section Syntax
@@ -350,7 +295,7 @@ The section is marked as read only.
 @node Z80 Opcodes
 @section Opcodes
 In line with common practice, Z80 mnemonics are used for the Z80,
-the Z180, eZ80 and the R800.
+Z80N, Z180, eZ80, Ascii R800 and the GameBoy Z80.
 
 In many instructions it is possible to use one of the half index
 registers (@samp{ixl},@samp{ixh},@samp{iyl},@samp{iyh}) in stead of an
@@ -376,17 +321,17 @@ This is equivalent to
 
 @example
 ld @var{r}, (ix+@var{d})
-@var{opc} @var{r}
+@var{op} @var{r}
 ld (ix+@var{d}), @var{r}
 @end example
 
-The operation @samp{@var{opc}} may be any of @samp{res @var{b},},
+The operation @samp{@var{op}} may be any of @samp{res @var{b},},
 @samp{set @var{b},}, @samp{rl}, @samp{rlc}, @samp{rr}, @samp{rrc},
 @samp{sla}, @samp{sli}, @samp{sra} and @samp{srl}, and the register
 @samp{@var{r}} may be any of @samp{a}, @samp{b}, @samp{c}, @samp{d},
 @samp{e}, @samp{h} and @samp{l}.
 
-@item @var{opc} (iy+@var{d}), @var{r}
+@item @var{op} (iy+@var{d}), @var{r}
 As above, but with @samp{iy} instead of @samp{ix}.
 @end table
 
diff --git a/gas/testsuite/gas/z80/ez80_adl_all.d b/gas/testsuite/gas/z80/ez80_adl_all.d
index 8d715c6..45793ac 100644
--- a/gas/testsuite/gas/z80/ez80_adl_all.d
+++ b/gas/testsuite/gas/z80/ez80_adl_all.d
@@ -1,4 +1,4 @@
-#as: -ez80-adl
+#as: -march=ez80+adl
 #objdump: -d
 #name: All eZ80 instructions in ADL cpu mode
 
diff --git a/gas/testsuite/gas/z80/ez80_adl_suf.d b/gas/testsuite/gas/z80/ez80_adl_suf.d
index e6d9d34..0e22362 100644
--- a/gas/testsuite/gas/z80/ez80_adl_suf.d
+++ b/gas/testsuite/gas/z80/ez80_adl_suf.d
@@ -1,4 +1,4 @@
-#as: -ez80-adl
+#as: -march=ez80+adl
 #objdump: -d
 #name: eZ80 instructions with sufficies in ADL cpu mode
 #source: ez80_isuf.s
diff --git a/gas/testsuite/gas/z80/ez80_pref_dis.d b/gas/testsuite/gas/z80/ez80_pref_dis.d
index d76e43f..517e2c9 100644
--- a/gas/testsuite/gas/z80/ez80_pref_dis.d
+++ b/gas/testsuite/gas/z80/ez80_pref_dis.d
@@ -1,5 +1,5 @@
 #name: multiple eZ80 opcode prefixes
-#as: -ez80
+#as: -march=ez80
 #objdump: -d
 
 .*:[     ]+file format (coff)|(elf32)\-z80
diff --git a/gas/testsuite/gas/z80/ez80_z80_all.d b/gas/testsuite/gas/z80/ez80_z80_all.d
index 0cf7f9a..ce69d25 100644
--- a/gas/testsuite/gas/z80/ez80_z80_all.d
+++ b/gas/testsuite/gas/z80/ez80_z80_all.d
@@ -1,4 +1,4 @@
-#as: -ez80
+#as: -march=ez80
 #objdump: -d
 #name: All eZ80 instructions in Z80 cpu mode
 
diff --git a/gas/testsuite/gas/z80/ez80_z80_suf.d b/gas/testsuite/gas/z80/ez80_z80_suf.d
index af35f0b..4fa7cd9c 100644
--- a/gas/testsuite/gas/z80/ez80_z80_suf.d
+++ b/gas/testsuite/gas/z80/ez80_z80_suf.d
@@ -1,4 +1,4 @@
-#as: -ez80
+#as: -march=ez80
 #objdump: -d
 #name: eZ80 instructions with sufficies in Z80 cpu mode
 #source: ez80_isuf.s
diff --git a/gas/testsuite/gas/z80/gbz80_all.d b/gas/testsuite/gas/z80/gbz80_all.d
index 0bb5db0..cfd416b 100644
--- a/gas/testsuite/gas/z80/gbz80_all.d
+++ b/gas/testsuite/gas/z80/gbz80_all.d
@@ -1,4 +1,4 @@
-#as: -gbz80
+#as: -march=gbz80
 #objdump: -d
 #name: GBZ80 instruction set
 
diff --git a/gas/testsuite/gas/z80/r800_extra.d b/gas/testsuite/gas/z80/r800_extra.d
index c700c1f..03a6401 100644
--- a/gas/testsuite/gas/z80/r800_extra.d
+++ b/gas/testsuite/gas/z80/r800_extra.d
@@ -1,4 +1,4 @@
-#as: -r800
+#as: -march=r800
 #objdump: -d
 #name: R800 specific instructions
 
diff --git a/gas/testsuite/gas/z80/r800_ii8.d b/gas/testsuite/gas/z80/r800_ii8.d
index c4b6ca2..e607e34 100644
--- a/gas/testsuite/gas/z80/r800_ii8.d
+++ b/gas/testsuite/gas/z80/r800_ii8.d
@@ -1,4 +1,4 @@
-#as: -r800
+#as: -march=r800
 #objdump: -d
 #name: halves of index register for R800
 #source: z80_ii8.s
diff --git a/gas/testsuite/gas/z80/r800_z80_doc.d b/gas/testsuite/gas/z80/r800_z80_doc.d
index 3a1d434..b5a0844 100644
--- a/gas/testsuite/gas/z80/r800_z80_doc.d
+++ b/gas/testsuite/gas/z80/r800_z80_doc.d
@@ -1,4 +1,4 @@
-#as: -r800
+#as: -march=r800
 #objdump: -d
 #name: All Z80 documented instructions for R800
 #source: z80_doc.s
diff --git a/gas/testsuite/gas/z80/sdcc.d b/gas/testsuite/gas/z80/sdcc.d
index 53c630b..340454d 100644
--- a/gas/testsuite/gas/z80/sdcc.d
+++ b/gas/testsuite/gas/z80/sdcc.d
@@ -1,12 +1,12 @@
 #name: SDCC compatibility mode
-#source: sdcc.s -z80 -sdcc
+#as: -sdcc
 #objdump: -d -j _CODE
 
 .*:[     ]+file format (coff)|(elf32)\-z80
 
 Disassembly of section _CODE:
 
-00000000 <_start>:
+0+0 <_start>:
 [   ]+0:[ 	]+21 04 00[    	]+ld hl,0x0004
 [   ]+3:[ 	]+8f[          	]+adc a,a
 [   ]+4:[ 	]+88[          	]+adc a,b
@@ -135,13 +135,14 @@ Disassembly of section _CODE:
 [  ]+cf:[ 	]+c3 7b 00[    	]+jp 0x007b
 [  ]+d2:[ 	]+c3 93 00[    	]+jp 0x0093
 [  ]+d5:[ 	]+c3 ab 00[    	]+jp 0x00ab
+0+d8 <_func>:
 [  ]+d8:[ 	]+21 00 00[    	]+ld hl,0x0000
 [  ]+db:[ 	]+36 00[       	]+ld \(hl\),0x00
 [  ]+dd:[ 	]+23[          	]+inc hl
 [  ]+de:[ 	]+36 00[       	]+ld \(hl\),0x00
 [  ]+e0:[ 	]+18 fb[       	]+jr 0x00dd
 
-000000e2 <_finish>:
+0+e2 <_finish>:
 [  ]+e2:[ 	]+fd 7e 02[    	]+ld a,\(iy\+2\)
 [  ]+e5:[ 	]+dd 77 ff[    	]+ld \(ix\-1\),a
 [  ]+e8:[ 	]+3a 34 12[    	]+ld a,\(0x1234\)
diff --git a/gas/testsuite/gas/z80/sdcc.s b/gas/testsuite/gas/z80/sdcc.s
index dae75c5..5fe9288 100644
--- a/gas/testsuite/gas/z80/sdcc.s
+++ b/gas/testsuite/gas/z80/sdcc.s
@@ -149,7 +149,7 @@ _start::
 	jp	500$
 	jp	600$
 	jp	700$
-.L_func:
+_func:
 	ld	hl,0
 	ld	(hl),#<function
 00100$:
diff --git a/gas/testsuite/gas/z80/z180.d b/gas/testsuite/gas/z80/z180.d
index 6f3f8f9..0f08b0e 100644
--- a/gas/testsuite/gas/z80/z180.d
+++ b/gas/testsuite/gas/z80/z180.d
@@ -1,4 +1,4 @@
-#as: -z180
+#as: -march=z180
 #objdump: -d
 #name: Z180 specific instructions
 
diff --git a/gas/testsuite/gas/z80/z180_z80_doc.d b/gas/testsuite/gas/z80/z180_z80_doc.d
index e6211b6..c7791ac 100644
--- a/gas/testsuite/gas/z80/z180_z80_doc.d
+++ b/gas/testsuite/gas/z80/z180_z80_doc.d
@@ -1,4 +1,4 @@
-#as: -z180
+#as: -march=z180
 #objdump: -d
 #name: All Z80 documented instructions for Z180
 #source: z80_doc.s
diff --git a/gas/testsuite/gas/z80/z80_doc.d b/gas/testsuite/gas/z80/z80_doc.d
index 935f68e..c179ab8 100644
--- a/gas/testsuite/gas/z80/z80_doc.d
+++ b/gas/testsuite/gas/z80/z80_doc.d
@@ -1,4 +1,4 @@
-#as: -z80 -without-inst=sli,op-ii-ld,idx-reg-halves,in-f-c,out-c-0
+#as: -march=z80-full
 #objdump: -d
 #name: All Z80 documented instructions
 
diff --git a/gas/testsuite/gas/z80/z80_ii8.d b/gas/testsuite/gas/z80/z80_ii8.d
index db668b6..96386df 100644
--- a/gas/testsuite/gas/z80/z80_ii8.d
+++ b/gas/testsuite/gas/z80/z80_ii8.d
@@ -1,4 +1,4 @@
-#as: --with-inst=idx-reg-halves
+#as: -march=z80-full+xyhl
 #objdump: -d
 #name: halves of index register
 
diff --git a/gas/testsuite/gas/z80/z80_in_f_c.d b/gas/testsuite/gas/z80/z80_in_f_c.d
index e9c2d91..6de0284 100644
--- a/gas/testsuite/gas/z80/z80_in_f_c.d
+++ b/gas/testsuite/gas/z80/z80_in_f_c.d
@@ -1,4 +1,4 @@
-#as: --with-inst=in-f-c
+#as: -march=z80-full+infc
 #objdump: -d
 #name: Z80 undocumented instruction IN F,(C)
 
diff --git a/gas/testsuite/gas/z80/z80_op_ii_ld.d b/gas/testsuite/gas/z80/z80_op_ii_ld.d
index 42d917a..55a5fc6 100644
--- a/gas/testsuite/gas/z80/z80_op_ii_ld.d
+++ b/gas/testsuite/gas/z80/z80_op_ii_ld.d
@@ -1,4 +1,4 @@
-#as: -z80 -with-inst=sli,op-ii-ld
+#as: -march=z80-full+sli+xdcb
 #objdump: -d
 #name: Z80 undocumented instructions DD/FD CB dis op
 
diff --git a/gas/testsuite/gas/z80/z80_out_c_0.d b/gas/testsuite/gas/z80/z80_out_c_0.d
index b600229..07bbc3c 100644
--- a/gas/testsuite/gas/z80/z80_out_c_0.d
+++ b/gas/testsuite/gas/z80/z80_out_c_0.d
@@ -1,4 +1,4 @@
-#as: --with-inst=out-c-0
+#as: -march=z80-full+outc0
 #objdump: -d
 #name: Z80 undocumented instruction OUT (C),0
 
diff --git a/gas/testsuite/gas/z80/z80_sli.d b/gas/testsuite/gas/z80/z80_sli.d
index af5cd96..2c0512a 100644
--- a/gas/testsuite/gas/z80/z80_sli.d
+++ b/gas/testsuite/gas/z80/z80_sli.d
@@ -1,4 +1,4 @@
-#as: --with-inst=sli
+#as: -march=z80-full+sli
 #objdump: -d
 #name: Z80 instruction SLI/SLL
 
diff --git a/gas/testsuite/gas/z80/z80n_all.d b/gas/testsuite/gas/z80/z80n_all.d
index 3412905..c5cb526 100644
--- a/gas/testsuite/gas/z80/z80n_all.d
+++ b/gas/testsuite/gas/z80/z80n_all.d
@@ -1,4 +1,4 @@
-#as: -z80n
+#as: -march=z80n
 #objdump: -d
 
 .*:[     ]+file format (coff|elf32)\-z80
diff --git a/gas/testsuite/gas/z80/z80n_reloc.d b/gas/testsuite/gas/z80/z80n_reloc.d
index 8fa78e1..699a186 100644
--- a/gas/testsuite/gas/z80/z80n_reloc.d
+++ b/gas/testsuite/gas/z80/z80n_reloc.d
@@ -1,4 +1,4 @@
-#as: -z80n
+#as: -march=z80n
 #source: z80n_all.s
 #objdump: -r
 #name: Z80N big-endian relocation