Implement BMI instructions.

10 files changed, 610 insertions, 18 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 63868a0..356c81d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Allow encoding 32/64bit
+	integer registers in VEX.vvvv.  Check register-only source
+	operand when two source operands are swapped.  Properly update
+	destination when two source operands are swapped.
+
 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas.c (parse_args): Update copyright to 2011.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7ca97a6..2e28d8e 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5310,16 +5310,34 @@ build_modrm_byte (void)
 	  if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
 	    {
 	      /* For instructions with VexNDS, the register-only
-		 source operand must be XMM or YMM register. It is
-		 encoded in VEX prefix.  We need to clear RegMem bit
-		 before calling operand_type_equal.  */
-	      i386_operand_type op = i.tm.operand_types[dest];
+		 source operand must be 32/64bit integer, XMM or
+		 YMM register.  It is encoded in VEX prefix.  We
+		 need to clear RegMem bit before calling
+		 operand_type_equal.  */
+
+	      i386_operand_type op;
+	      unsigned int vvvv;
+
+	      /* Check register-only source operand when two source
+		 operands are swapped.  */
+	      if (!i.tm.operand_types[source].bitfield.baseindex
+		  && i.tm.operand_types[dest].bitfield.baseindex)
+		{
+		  vvvv = source;
+		  source = dest;
+		}
+	      else
+		vvvv = dest;
+
+	      op = i.tm.operand_types[vvvv];
 	      op.bitfield.regmem = 0;
 	      if ((dest + 1) >= i.operands
-		  || (!operand_type_equal (&op, &regxmm)
+		  || (op.bitfield.reg32 != 1
+		      && !op.bitfield.reg64 != 1
+		      && !operand_type_equal (&op, &regxmm)
 		      && !operand_type_equal (&op, &regymm)))
 		abort ();
-	      i.vex.register_specifier = i.op[dest].regs;
+	      i.vex.register_specifier = i.op[vvvv].regs;
 	      dest++;
 	    }
 	}
@@ -5647,30 +5665,51 @@ build_modrm_byte (void)
 		}
 	      else
 		{
-		  vex_reg = op + 1;
-		  gas_assert (vex_reg < i.operands);
+		  /* Check register-only source operand when two source
+		     operands are swapped.  */
+		  if (!i.tm.operand_types[op].bitfield.baseindex
+		      && i.tm.operand_types[op + 1].bitfield.baseindex)
+		    {
+		      vex_reg = op;
+		      op += 2;
+		      gas_assert (mem == (vex_reg + 1)
+				  && op < i.operands);
+		    }
+		  else
+		    {
+		      vex_reg = op + 1;
+		      gas_assert (vex_reg < i.operands);
+		    }
 		}
 	    }
 	  else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
 	    {
-	      /* For instructions with VexNDD, there should be
-		 no memory operand and the register destination
+	      /* For instructions with VexNDD, the register destination
 		 is encoded in VEX prefix.  */
-	      gas_assert (i.mem_operands == 0
-			  && (op + 2) == i.operands);
-	      vex_reg = op + 1;
+	      if (i.mem_operands == 0)
+		{
+		  /* There is no memory operand.  */
+		  gas_assert ((op + 2) == i.operands);
+		  vex_reg = op + 1;
+		}
+	      else
+		{ 
+		  /* There are only 2 operands.  */
+		  gas_assert (op < 2 && i.operands == 2);
+		  vex_reg = 1;
+		}
 	    }
 	  else
 	    gas_assert (op < i.operands);
 
 	  if (vex_reg != (unsigned int) ~0)
 	    {
-	      gas_assert (i.reg_operands == 2);
+	      i386_operand_type *type = &i.tm.operand_types[vex_reg];
 
-	      if (!operand_type_equal (&i.tm.operand_types[vex_reg],
-				       &regxmm)
-		  && !operand_type_equal (&i.tm.operand_types[vex_reg],
-					  &regymm))
+	      if (type->bitfield.reg32 != 1
+		  && type->bitfield.reg64 != 1
+		  && !operand_type_equal (type, &regxmm)
+		  && !operand_type_equal (type, &regymm))
 		abort ();
 
 	      i.vex.register_specifier = i.op[vex_reg].regs;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0aeed72..b8ad2c3 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/bmi-intel.d: New.
+	* gas/i386/bmi.d: Likewise.
+	* gas/i386/bmi.s: Likewise.
+	* gas/i386/x86-64-bmi-intel.d: Likewise.
+	* gas/i386/x86-64-bmi.d: Likewise.
+	* gas/i386/x86-64-bmi.s: Likewise.
+
+	* gas/i386/i386.exp: Run bmi, bmi-intel, x86-64-bmi and
+	x86-64-bmi-intel.
+
 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/ilp32/lns/lns-common-1.d: Also expect .zdebug in
diff --git a/gas/testsuite/gas/i386/bmi-intel.d b/gas/testsuite/gas/i386/bmi-intel.d
new file mode 100644
index 0000000..38eb5b4
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi-intel.d
@@ -0,0 +1,47 @@
+#as: 
+#objdump: -dwMintel
+#name: i386 BMI insns (Intel disassembly)
+#source: bmi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  bx,ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[ecx\],ebx
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  ebx,eax
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  bx,ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[ecx\],ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[ecx\],ebx
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  ebx,eax
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[ecx\]
+#pass
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1cded8b
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,46 @@
+#as: 
+#objdump: -dw
+#name: i386 BMI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%ecx\),%bx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%ecx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  %eax,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%ecx\),%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%ecx\),%bx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%ecx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%ecx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  %eax,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%ecx\),%ebx
+#pass
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..fe22145
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,58 @@
+# Check 32bit BMI instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+# Test for op r16, r/m16
+	tzcnt %ax,%bx
+	tzcnt (%ecx),%bx
+
+# Test for op r32, r32, r/m32
+	andn %eax,%ebx,%esi
+	andn (%ecx),%ebx,%esi
+
+# Test for op r32, r/m32, r32
+	bextr %eax,%ebx,%esi
+	bextr %ebx,(%ecx),%esi
+
+# Test for op r32, r/m32
+	tzcnt %eax,%ebx
+	tzcnt (%ecx),%ebx
+	blsi %eax,%ebx
+	blsi (%ecx),%ebx
+	blsmsk %eax,%ebx
+	blsmsk (%ecx),%ebx
+	blsr %eax,%ebx
+	blsr (%ecx),%ebx
+
+	.intel_syntax noprefix
+
+# Test for op r16, r/m16
+	tzcnt bx,ax
+	tzcnt bx,WORD PTR [ecx]
+	tzcnt bx,[ecx]
+
+# Test for op r32, r32, r/m32
+	andn esi,ebx,eax
+	andn esi,ebx,DWORD PTR [ecx]
+	andn esi,ebx,[ecx]
+
+# Test for op r32, r/m32, r32
+	bextr esi,ebx,eax
+	bextr esi,DWORD PTR [ecx],ebx
+	bextr esi,[ecx],ebx
+
+# Test for op r32, r/m32
+	tzcnt ebx,eax
+	tzcnt ebx,DWORD PTR [ecx]
+	tzcnt ebx,[ecx]
+	blsi ebx,eax
+	blsi ebx,DWORD PTR [ecx]
+	blsi ebx,[ecx]
+	blsmsk ebx,eax
+	blsmsk ebx,DWORD PTR [ecx]
+	blsmsk ebx,[ecx]
+	blsr ebx,eax
+	blsr ebx,DWORD PTR [ecx]
+	blsr ebx,[ecx]
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..2d36fae 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
+    run_dump_test "bmi"
+    run_dump_test "bmi-intel"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -372,6 +374,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
+    run_dump_test "x86-64-bmi"
+    run_dump_test "x86-64-bmi-intel"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-bmi-intel.d b/gas/testsuite/gas/i386/x86-64-bmi-intel.d
new file mode 100644
index 0000000..09cfa00
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi-intel.d
@@ -0,0 +1,119 @@
+#as: 
+#objdump: -dwMintel
+#name: x86-64 BMI insns (Intel disassembly)
+#source: x86-64-bmi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  bx,ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 39    	tzcnt  r15w,WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 42 00 f2 d1       	andn   r10d,r15d,r9d
+[ 	]*[a-f0-9]+:	c4 62 00 f2 11       	andn   r10d,r15d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[rcx\],ebx
+[ 	]*[a-f0-9]+:	c4 42 30 f7 d7       	bextr  r10d,r15d,r9d
+[ 	]*[a-f0-9]+:	c4 62 30 f7 11       	bextr  r10d,DWORD PTR \[rcx\],r9d
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  ebx,eax
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 44 0f bc 39       	tzcnt  r15d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 19       	blsi   r15d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 11       	blsmsk r15d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 09       	blsr   r15d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 f0       	andn   rsi,rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   rsi,rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 42 80 f2 d1       	andn   r10,r15,r9
+[ 	]*[a-f0-9]+:	c4 62 80 f2 11       	andn   r10,r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 f3       	bextr  rsi,rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  rsi,QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	c4 42 b0 f7 d7       	bextr  r10,r15,r9
+[ 	]*[a-f0-9]+:	c4 62 b0 f7 11       	bextr  r10,QWORD PTR \[rcx\],r9
+[ 	]*[a-f0-9]+:	f3 48 0f bc d8       	tzcnt  rbx,rax
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 4d 0f bc f9       	tzcnt  r15,r9
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 39       	tzcnt  r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d8       	blsi   rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d9       	blsi   r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 19       	blsi   r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d0       	blsmsk rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 11       	blsmsk r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 c8       	blsr   rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 c9       	blsr   r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 09       	blsr   r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  bx,ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 11    	tzcnt  r10w,WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  bx,WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 42 28 f2 f9       	andn   r15d,r10d,r9d
+[ 	]*[a-f0-9]+:	c4 62 28 f2 39       	andn   r15d,r10d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   esi,ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  esi,ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[rcx\],ebx
+[ 	]*[a-f0-9]+:	c4 42 30 f7 fa       	bextr  r15d,r10d,r9d
+[ 	]*[a-f0-9]+:	c4 62 30 f7 39       	bextr  r15d,DWORD PTR \[rcx\],r9d
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  esi,DWORD PTR \[rcx\],ebx
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  ebx,eax
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 44 0f bc 11       	tzcnt  r10d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 19       	blsi   r10d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 11       	blsmsk r10d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   ebx,eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 09       	blsr   r10d,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   ebx,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 f0       	andn   rsi,rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   rsi,rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 42 80 f2 d1       	andn   r10,r15,r9
+[ 	]*[a-f0-9]+:	c4 62 80 f2 11       	andn   r10,r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   rsi,rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 f3       	bextr  rsi,rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  rsi,QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	c4 42 b0 f7 d7       	bextr  r10,r15,r9
+[ 	]*[a-f0-9]+:	c4 62 b0 f7 11       	bextr  r10,QWORD PTR \[rcx\],r9
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  rsi,QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 48 0f bc d8       	tzcnt  rbx,rax
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 4d 0f bc f9       	tzcnt  r15,r9
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 39       	tzcnt  r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d8       	blsi   rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d9       	blsi   r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 19       	blsi   r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d0       	blsmsk rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 11       	blsmsk r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 c8       	blsr   rbx,rax
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   rbx,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 c9       	blsr   r15,r9
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 09       	blsr   r15,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   rbx,QWORD PTR \[rcx\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..9b59d10
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,118 @@
+#as: 
+#objdump: -dw
+#name: x86-64 BMI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%rcx\),%bx
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 39    	tzcnt  \(%rcx\),%r15w
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%rcx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 42 00 f2 d1       	andn   %r9d,%r15d,%r10d
+[ 	]*[a-f0-9]+:	c4 62 00 f2 11       	andn   \(%rcx\),%r15d,%r10d
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%rcx\),%esi
+[ 	]*[a-f0-9]+:	c4 42 30 f7 d7       	bextr  %r9d,%r15d,%r10d
+[ 	]*[a-f0-9]+:	c4 62 30 f7 11       	bextr  %r9d,\(%rcx\),%r10d
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  %eax,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	f3 44 0f bc 39       	tzcnt  \(%rcx\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 19       	blsi   \(%rcx\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 11       	blsmsk \(%rcx\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 00 f3 09       	blsr   \(%rcx\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 f0       	andn   %rax,%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   \(%rcx\),%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 42 80 f2 d1       	andn   %r9,%r15,%r10
+[ 	]*[a-f0-9]+:	c4 62 80 f2 11       	andn   \(%rcx\),%r15,%r10
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 f3       	bextr  %rax,%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  %rax,\(%rcx\),%rsi
+[ 	]*[a-f0-9]+:	c4 42 b0 f7 d7       	bextr  %r9,%r15,%r10
+[ 	]*[a-f0-9]+:	c4 62 b0 f7 11       	bextr  %r9,\(%rcx\),%r10
+[ 	]*[a-f0-9]+:	f3 48 0f bc d8       	tzcnt  %rax,%rbx
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	f3 4d 0f bc f9       	tzcnt  %r9,%r15
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 39       	tzcnt  \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d8       	blsi   %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d9       	blsi   %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 19       	blsi   \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d0       	blsmsk %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 11       	blsmsk \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 c8       	blsr   %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 c9       	blsr   %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 09       	blsr   \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%rcx\),%bx
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 11    	tzcnt  \(%rcx\),%r10w
+[ 	]*[a-f0-9]+:	66 f3 0f bc 19       	tzcnt  \(%rcx\),%bx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f0       	andn   %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%rcx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 42 28 f2 f9       	andn   %r9d,%r10d,%r15d
+[ 	]*[a-f0-9]+:	c4 62 28 f2 39       	andn   \(%rcx\),%r10d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 31       	andn   \(%rcx\),%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 f3       	bextr  %eax,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%rcx\),%esi
+[ 	]*[a-f0-9]+:	c4 42 30 f7 fa       	bextr  %r9d,%r10d,%r15d
+[ 	]*[a-f0-9]+:	c4 62 30 f7 39       	bextr  %r9d,\(%rcx\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 31       	bextr  %ebx,\(%rcx\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bc d8          	tzcnt  %eax,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	f3 44 0f bc 11       	tzcnt  \(%rcx\),%r10d
+[ 	]*[a-f0-9]+:	f3 0f bc 19          	tzcnt  \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d8       	blsi   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 19       	blsi   \(%rcx\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 19       	blsi   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 d0       	blsmsk %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 11       	blsmsk \(%rcx\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c8       	blsr   %eax,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 28 f3 09       	blsr   \(%rcx\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 09       	blsr   \(%rcx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 f0       	andn   %rax,%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   \(%rcx\),%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 42 80 f2 d1       	andn   %r9,%r15,%r10
+[ 	]*[a-f0-9]+:	c4 62 80 f2 11       	andn   \(%rcx\),%r15,%r10
+[ 	]*[a-f0-9]+:	c4 e2 e0 f2 31       	andn   \(%rcx\),%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 f3       	bextr  %rax,%rbx,%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  %rax,\(%rcx\),%rsi
+[ 	]*[a-f0-9]+:	c4 42 b0 f7 d7       	bextr  %r9,%r15,%r10
+[ 	]*[a-f0-9]+:	c4 62 b0 f7 11       	bextr  %r9,\(%rcx\),%r10
+[ 	]*[a-f0-9]+:	c4 e2 f8 f7 31       	bextr  %rax,\(%rcx\),%rsi
+[ 	]*[a-f0-9]+:	f3 48 0f bc d8       	tzcnt  %rax,%rbx
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	f3 4d 0f bc f9       	tzcnt  %r9,%r15
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 39       	tzcnt  \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	f3 48 0f bc 19       	tzcnt  \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d8       	blsi   %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d9       	blsi   %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 19       	blsi   \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 19       	blsi   \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 d0       	blsmsk %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 11       	blsmsk \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 11       	blsmsk \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 c8       	blsr   %rax,%rbx
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   \(%rcx\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 c9       	blsr   %r9,%r15
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 09       	blsr   \(%rcx\),%r15
+[ 	]*[a-f0-9]+:	c4 e2 e0 f3 09       	blsr   \(%rcx\),%rbx
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..ef222c9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,142 @@
+# Check 64bit BMI instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+# Test for op r16, r/m16
+	tzcnt %ax,%bx
+	tzcnt (%rcx),%bx
+	tzcnt (%rcx),%r15w
+
+# Test for op r32, r32, r/m32
+	andn %eax,%ebx,%esi
+	andn (%rcx),%ebx,%esi
+	andn %r9d,%r15d,%r10d
+	andn (%rcx),%r15d,%r10d
+
+# Test for op r32, r/m32, r32
+	bextr %eax,%ebx,%esi
+	bextr %ebx,(%rcx),%esi
+	bextr %r9d,%r15d,%r10d
+	bextr %r9d,(%rcx),%r10d
+
+# Test for op r32, r/m32
+	tzcnt %eax,%ebx
+	tzcnt (%rcx),%ebx
+	tzcnt (%rcx),%r15d
+	blsi %eax,%ebx
+	blsi (%rcx),%ebx
+	blsi (%rcx),%r15d
+	blsmsk %eax,%ebx
+	blsmsk (%rcx),%ebx
+	blsmsk (%rcx),%r15d
+	blsr %eax,%ebx
+	blsr (%rcx),%ebx
+	blsr (%rcx),%r15d
+
+# Test for op r64, r64, r/m64
+	andn %rax,%rbx,%rsi
+	andn (%rcx),%rbx,%rsi
+	andn %r9,%r15,%r10
+	andn (%rcx),%r15,%r10
+
+# Test for op r64, r/m64, r64
+	bextr %rax,%rbx,%rsi
+	bextr %rax,(%rcx),%rsi
+	bextr %r9,%r15,%r10
+	bextr %r9,(%rcx),%r10
+
+# Test for op r64, r/m64
+	tzcnt %rax,%rbx
+	tzcnt (%rcx),%rbx
+	tzcnt %r9,%r15
+	tzcnt (%rcx),%r15
+	blsi %rax,%rbx
+	blsi (%rcx),%rbx
+	blsi %r9,%r15
+	blsi (%rcx),%r15
+	blsmsk %rax,%rbx
+	blsmsk (%rcx),%rbx
+	blsmsk %r9,%r15
+	blsmsk (%rcx),%r15
+	blsr %rax,%rbx
+	blsr (%rcx),%rbx
+	blsr %r9,%r15
+	blsr (%rcx),%r15
+
+	.intel_syntax noprefix
+
+# Test for op r16, r/m16
+	tzcnt bx,ax
+	tzcnt bx,WORD PTR [rcx]
+	tzcnt r10w,WORD PTR [rcx]
+	tzcnt bx,[rcx]
+
+# Test for op r32, r32, r/m32
+	andn esi,ebx,eax
+	andn esi,ebx,DWORD PTR [rcx]
+	andn r15d,r10d,r9d
+	andn r15d,r10d,DWORD PTR [rcx]
+	andn esi,ebx,[rcx]
+
+# Test for op r32, r/m32, r32
+	bextr esi,ebx,eax
+	bextr esi,DWORD PTR [rcx],ebx
+	bextr r15d,r10d,r9d
+	bextr r15d,DWORD PTR [rcx],r9d
+	bextr esi,[rcx],ebx
+
+# Test for op r32, r/m32
+	tzcnt ebx,eax
+	tzcnt ebx,DWORD PTR [rcx]
+	tzcnt r10d,DWORD PTR [rcx]
+	tzcnt ebx,[rcx]
+	blsi ebx,eax
+	blsi ebx,DWORD PTR [rcx]
+	blsi r10d,DWORD PTR [rcx]
+	blsi ebx,[rcx]
+	blsmsk ebx,eax
+	blsmsk ebx,DWORD PTR [rcx]
+	blsmsk r10d,DWORD PTR [rcx]
+	blsmsk ebx,[rcx]
+	blsr ebx,eax
+	blsr ebx,DWORD PTR [rcx]
+	blsr r10d,DWORD PTR [rcx]
+	blsr ebx,[rcx]
+
+# Test for op r64, r64, r/m64
+	andn rsi,rbx,rax
+	andn rsi,rbx,QWORD PTR [rcx]
+	andn r10,r15,r9
+	andn r10,r15,QWORD PTR [rcx]
+	andn rsi,rbx,[rcx]
+
+# Test for op r64, r/m64, r64
+	bextr rsi,rbx,rax
+	bextr rsi,QWORD PTR [rcx],rax
+	bextr r10,r15,r9
+	bextr r10,QWORD PTR [rcx],r9
+	bextr rsi,[rcx],rax
+
+# Test for op r64, r/m64
+	tzcnt rbx,rax
+	tzcnt rbx,QWORD PTR [rcx]
+	tzcnt r15,r9
+	tzcnt r15,QWORD PTR [rcx]
+	tzcnt rbx,[rcx]
+	blsi rbx,rax
+	blsi rbx,QWORD PTR [rcx]
+	blsi r15,r9
+	blsi r15,QWORD PTR [rcx]
+	blsi rbx,[rcx]
+	blsmsk rbx,rax
+	blsmsk rbx,QWORD PTR [rcx]
+	blsmsk r15,r9
+	blsmsk r15,QWORD PTR [rcx]
+	blsmsk rbx,[rcx]
+	blsr rbx,rax
+	blsr rbx,QWORD PTR [rcx]
+	blsr r15,r9
+	blsr r15,QWORD PTR [rcx]
+	blsr rbx,[rcx]