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authorJim Wilson <jimw@sifive.com>2018-05-08 15:46:19 -0700
committerJim Wilson <jimw@sifive.com>2018-05-08 15:46:19 -0700
commite6f372ba661bb0d8eec1e22a6dc1ad9937336e4d (patch)
tree1e9fa44730d068196b581e511fe544517b1a7d6d /gas
parent7402fbcae1c282e27aafd5c5c90aca7eabbdf45c (diff)
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RISC-V: Add missing hint instructions from RV128I.
gas/ * testsuite/gas/riscv/c-zero-imm.d: Add more tests. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled future test for RV128 support. * testsuite/gas/riscv/c-zero-reg.s: Likewise. include/ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. (MATCH_C_SRAI64, MASK_C_SRAI64): New. (MATCH_C_SLLI64, MASK_C_SLLI64): New. opcodes/ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. (match_c_slli64, match_srxi_as_c_srxi): New. (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. <c.slli, c.srli, c.srai>: Use match_s_slli. <c.slli64, c.srli64, c.srai64>: New.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/testsuite/gas/riscv/c-zero-imm.d6
-rw-r--r--gas/testsuite/gas/riscv/c-zero-imm.s8
-rw-r--r--gas/testsuite/gas/riscv/c-zero-reg.d2
-rw-r--r--gas/testsuite/gas/riscv/c-zero-reg.s4
5 files changed, 26 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 971e42a..88ab077 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2018-05-08 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/gas/riscv/c-zero-imm.d: Add more tests.
+ * testsuite/gas/riscv/c-zero-imm.s: Likewise.
+ * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
+ future test for RV128 support.
+ * testsuite/gas/riscv/c-zero-reg.s: Likewise.
+
2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.d b/gas/testsuite/gas/riscv/c-zero-imm.d
index c138966..97b845d 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm.d
@@ -14,4 +14,10 @@ Disassembly of section .text:
[ ]+8:[ ]+0001[ ]+nop
[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
+[ ]+10:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0
+[ ]+14:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0
+[ ]+18:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0
+[ ]+1c:[ ]+0682[ ]+c.slli64[ ]+a3
+[ ]+1e:[ ]+8301[ ]+c.srli64[ ]+a4
+[ ]+20:[ ]+8781[ ]+c.srai64[ ]+a5
#...
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.s b/gas/testsuite/gas/riscv/c-zero-imm.s
index a07baa4..b0f4710 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.s
+++ b/gas/testsuite/gas/riscv/c-zero-imm.s
@@ -9,3 +9,11 @@
addi a4,a4,0
# These are hints.
c.addi a5,0
+ # Don't let these compress to hints.
+ slli a0, a0, 0
+ srli a1, a1, 0
+ srai a2, a2, 0
+ # These are hints.
+ c.slli64 a3
+ c.srli64 a4
+ c.srai64 a5
diff --git a/gas/testsuite/gas/riscv/c-zero-reg.d b/gas/testsuite/gas/riscv/c-zero-reg.d
index 2daf896..02d5978 100644
--- a/gas/testsuite/gas/riscv/c-zero-reg.d
+++ b/gas/testsuite/gas/riscv/c-zero-reg.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
[ ]+8:[ ]+9006[ ]+c.add[ ]+zero,ra
[ ]+a:[ ]+00500013[ ]+li[ ]+zero,5
[ ]+e:[ ]+00006037[ ]+lui[ ]+zero,0x6
-[ ]+12:[ ]+00709013[ ]+slli[ ]+zero,ra,0x7
+[ ]+12:[ ]+00701013[ ]+slli[ ]+zero,zero,0x7
[ ]+16:[ ]+00008013[ ]+mv[ ]+zero,ra
[ ]+1a:[ ]+00100033[ ]+add[ ]+zero,zero,ra
#...
diff --git a/gas/testsuite/gas/riscv/c-zero-reg.s b/gas/testsuite/gas/riscv/c-zero-reg.s
index 414c8a4..4e39030 100644
--- a/gas/testsuite/gas/riscv/c-zero-reg.s
+++ b/gas/testsuite/gas/riscv/c-zero-reg.s
@@ -8,6 +8,8 @@
# Don't let these compress to hints.
li x0, 5
lui x0, 6
- slli x0, x1, 7
+ slli x0, x0, 7
mv x0, x1
add x0, x0, x1
+# RV128 support not implemented yet.
+# slli x0, x0, 64