RISC-V: Add support for the Zvbb ISA extension

Zvbb is part of the vector crypto extensions.

This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbb.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
	string directive.
	(riscv_ip): Likewise.
	* testsuite/gas/riscv/zvbb.d: New test.
	* testsuite/gas/riscv/zvbb.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
	(MASK_VANDN_VV): New.
	(MATCH_VANDN_VX): New.
	(MASK_VANDN_VX): New.
	(MATCH_VBREV8_V): New.
	(MASK_VBREV8_V): New.
	(MATCH_VBREV_V): New.
	(MASK_VBREV_V): New.
	(MATCH_VCLZ_V): New.
	(MASK_VCLZ_V): New.
	(MATCH_VCPOP_V): New.
	(MASK_VCPOP_V): New.
	(MATCH_VCTZ_V): New.
	(MASK_VCTZ_V): New.
	(MATCH_VREV8_V): New.
	(MASK_VREV8_V): New.
	(MATCH_VROL_VV): New.
	(MASK_VROL_VV): New.
	(MATCH_VROL_VX): New.
	(MASK_VROL_VX): New.
	(MATCH_VROR_VI): New.
	(MASK_VROR_VI): New.
	(MATCH_VROR_VV): New.
	(MASK_VROR_VV): New.
	(MATCH_VROR_VX): New.
	(MASK_VROR_VX): New.
	(MATCH_VWSLL_VI): New.
	(MASK_VWSLL_VI): New.
	(MATCH_VWSLL_VV): New.
	(MASK_VWSLL_VV): New.
	(MATCH_VWSLL_VX): New.
	(MASK_VWSLL_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
	(ENCODE_RVV_VI_UIMM6): New.
	(enum riscv_insn_class): Add instruction class for Zvbb.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add 'l' as new format string
	directive.
	* riscv-opc.c: Add Zvbb instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

3 files changed, 90 insertions, 0 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 6bd3b2f..297bb9b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1341,6 +1341,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'i':
 	    case 'j':
 	    case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+	    case 'l': used_bits |= ENCODE_RVV_VI_UIMM6 (-1U); break;
 	    case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
 	    case 'M': break; /* Macro operand, must be a mask register.  */
 	    case 'T': break; /* Macro operand, must be a vector register.  */
@@ -3069,6 +3070,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  asarg = expr_parse_end;
 		  continue;
 
+		case 'l': /* 6-bit vector arith unsigned immediate */
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  if (imm_expr->X_add_number < 0
+		      || imm_expr->X_add_number >= 64)
+		    as_bad (_("bad value for vector immediate field, "
+			      "value must be 0...63"));
+		  ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
+		  imm_expr->X_op = O_absent;
+		  asarg = expr_parse_end;
+		  continue;
+
 		case 'm': /* optional vector mask */
 		  if (*asarg == '\0')
 		    {
diff --git a/gas/testsuite/gas/riscv/zvbb.d b/gas/testsuite/gas/riscv/zvbb.d
new file mode 100644
index 0000000..c6c9df5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.d
@@ -0,0 +1,43 @@
+#as: -march=rv64gc_zvbb
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+06860257[ 	]+vandn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+04860257[ 	]+vandn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0685c257[ 	]+vandn.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0485c257[ 	]+vandn.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a852257[ 	]+vbrev.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48852257[ 	]+vbrev.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a842257[ 	]+vbrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48842257[ 	]+vbrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a862257[ 	]+vclz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48862257[ 	]+vclz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a86a257[ 	]+vctz.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4886a257[ 	]+vctz.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a872257[ 	]+vcpop.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48872257[ 	]+vcpop.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+56860257[ 	]+vrol.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+54860257[ 	]+vrol.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5685c257[ 	]+vrol.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5485c257[ 	]+vrol.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52860257[ 	]+vror.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+50860257[ 	]+vror.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5285c257[ 	]+vror.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5085c257[ 	]+vror.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52803257[ 	]+vror.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+548fb257[ 	]+vror.vi[ 	]+v4,v8,63,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6860257[ 	]+vwsll.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d4860257[ 	]+vwsll.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d685c257[ 	]+vwsll.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+d485c257[ 	]+vwsll.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d6803257[ 	]+vwsll.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+d48fb257[ 	]+vwsll.vi[ 	]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvbb.s b/gas/testsuite/gas/riscv/zvbb.s
new file mode 100644
index 0000000..7a666ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.s
@@ -0,0 +1,34 @@
+	vandn.vv v4, v8, v12
+	vandn.vv v4, v8, v12, v0.t
+	vandn.vx v4, v8, a1
+	vandn.vx v4, v8, a1, v0.t
+	vbrev.v v4, v8
+	vbrev.v v4, v8, v0.t
+	vbrev8.v v4, v8
+	vbrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vclz.v v4, v8
+	vclz.v v4, v8, v0.t
+	vctz.v v4, v8
+	vctz.v v4, v8, v0.t
+	vcpop.v v4, v8
+	vcpop.v v4, v8, v0.t
+	vrol.vv v4, v8, v12
+	vrol.vv v4, v8, v12, v0.t
+	vrol.vx v4, v8, a1
+	vrol.vx v4, v8, a1, v0.t
+	vror.vv v4, v8, v12
+	vror.vv v4, v8, v12, v0.t
+	vror.vx v4, v8, a1
+	vror.vx v4, v8, a1, v0.t
+	vror.vi v4, v8, 0
+	vror.vi v4, v8, 63, v0.t
+	vwsll.vv v4, v8, v12
+	vwsll.vv v4, v8, v12, v0.t
+	vwsll.vx v4, v8, a1
+	vwsll.vx v4, v8, a1, v0.t
+	vwsll.vi v4, v8, 0
+	vwsll.vi v4, v8, 31, v0.t