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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-16 17:01:50 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | c0fbed64079541e614775f9f4f0354a705c13f8a (patch) | |
| tree | 245366add63ee59e2315ff15723822aef2a855b1 /gas | |
| parent | a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0 (diff) | |
| download | fsf-binutils-gdb-c0fbed64079541e614775f9f4f0354a705c13f8a.zip fsf-binutils-gdb-c0fbed64079541e614775f9f4f0354a705c13f8a.tar.gz fsf-binutils-gdb-c0fbed64079541e614775f9f4f0354a705c13f8a.tar.bz2 | |
aarch64: Add xs variants of tlbip operands
The 2020 Architecture Extensions to the Arm A-profile architecture
added FEAT_XS, the XS attribute feature, giving cores the ability to
identify devices which can be subject to long response delays. TLB
invalidate (TLBI) operations and barriers can also be annotated with
this attribute[1].
With the introduction of the 128-bit translation tables with the
Armv8.9-a/Armv9.4-a Translation Hardening Extension, a series of new
TLB invalidate operations are introduced which make use of this
extension. These are added to aarch64_sys_regs_tlbi[] for use
with the `tlbip' insn.
[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020
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