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| author | Nathan Huckleberry <nhuck@google.com> | 2023-06-30 22:43:40 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:34 -0600 |
| commit | c0a98a853d5ccde35dca20ad5d7cea0a70e16d56 (patch) | |
| tree | 5a5c318686f441523224c6657ee51419069c38ff /gas | |
| parent | c8cb37347fde3ae12c943c2133a1043eece4c127 (diff) | |
| download | fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.zip fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.gz fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.bz2 | |
RISC-V: Add support for the Zvbc extension
Zvbc is part of the crypto vector extensions.
This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbc.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvbc.d: New test.
* testsuite/gas/riscv/zvbc.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
(MASK_VCLMUL_VV): New.
(MATCH_VCLMUL_VX): New.
(MASK_VCLMUL_VX): New.
(MATCH_VCLMULH_VV): New.
(MASK_VCLMULH_VV): New.
(MATCH_VCLMULH_VX): New.
(MASK_VCLMULH_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvbc.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvbc instruction.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/zvbc.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvbc.s | 8 |
2 files changed, 24 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d new file mode 100644 index 0000000..d9213b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvbc.d @@ -0,0 +1,16 @@ +#as: -march=rv64gc_zvbc +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s new file mode 100644 index 0000000..c302d1e --- /dev/null +++ b/gas/testsuite/gas/riscv/zvbc.s @@ -0,0 +1,8 @@ + vclmul.vv v4, v8, v12 + vclmul.vv v4, v8, v12, v0.t + vclmul.vx v4, v8, a1 + vclmul.vx v4, v8, a1, v0.t + vclmulh.vv v4, v8, v12 + vclmulh.vv v4, v8, v12, v0.t + vclmulh.vx v4, v8, a1 + vclmulh.vx v4, v8, a1, v0.t |