aarch64: Add BC instruction

This patch adds support for the Armv8.8-A BC instruction.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en]

include/
	* opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro.
	(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC.

opcodes/
	* aarch64-tbl.h (aarch64_feature_hbc): New variable.
	(HBC, HBC_INSN): New macros.
	(aarch64_opcode_table): Add BC.C.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document +hbc.
	* config/tc-aarch64.c (aarch64_features): Add "hbc".
	* testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test.
	* testsuite/gas/aarch64/hbc-invalid.s,
	testsuite/gas/aarch64/hbc-invalid.l,
	testsuite/gas/aarch64/hbc-invalid.d: New test.

7 files changed, 90 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ea65da5..7277f38 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -9980,6 +9980,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"mops",		AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0),
 			AARCH64_ARCH_NONE},
+  {"hbc",		AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 7edccce..29bfd49 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -183,6 +183,8 @@ automatically cause those extensions to be disabled.
  @tab Enable ARMv8.2 16-bit floating-point support.  This implies @code{fp}.
 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable floating-point extensions.
+@item @code{hbc} @tab @tab Armv8.8-A or later
+ @tab Enable Armv8.8-A hinted conditional branch instructions
 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
  @tab Enable Int8 Matrix Multiply extension.
 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
diff --git a/gas/testsuite/gas/aarch64/hbc-invalid.d b/gas/testsuite/gas/aarch64/hbc-invalid.d
new file mode 100644
index 0000000..f243de5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/hbc-invalid.d
@@ -0,0 +1 @@
+#error_output: hbc-invalid.l
diff --git a/gas/testsuite/gas/aarch64/hbc-invalid.l b/gas/testsuite/gas/aarch64/hbc-invalid.l
new file mode 100644
index 0000000..aef7a21
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/hbc-invalid.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:4: Error: selected processor does not support `bc.eq 1b'
+[^:]*:8: Error: selected processor does not support `bc.eq 1b'
diff --git a/gas/testsuite/gas/aarch64/hbc-invalid.s b/gas/testsuite/gas/aarch64/hbc-invalid.s
new file mode 100644
index 0000000..bc22087
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/hbc-invalid.s
@@ -0,0 +1,8 @@
+	.arch	armv8.7-a
+
+1:
+	bc.eq	1b
+
+	.arch	armv8.7-a+mops
+
+	bc.eq	1b
diff --git a/gas/testsuite/gas/aarch64/hbc.d b/gas/testsuite/gas/aarch64/hbc.d
new file mode 100644
index 0000000..baf963d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/hbc.d
@@ -0,0 +1,37 @@
+# objdump: -dr
+
+.*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*:	54000010 	bc\.eq	0 <\.text>  // bc\.none
+[^:]*:	54fffff1 	bc\.ne	0 <\.text>  // bc\.any
+[^:]*:	54ffffd9 	bc\.ls	0 <\.text>  // bc\.plast
+[^:]*:	54ffffb3 	bc\.cc	0 <\.text>  // bc\.lo, bc\.ul, bc\.last
+[^:]*:	54ffff98 	bc\.hi	0 <\.text>  // bc\.pmore
+[^:]*:	54ffff72 	bc\.cs	0 <\.text>  // bc\.hs, bc\.nlast
+[^:]*:	54ffff58 	bc\.hi	0 <\.text>  // bc\.pmore
+[^:]*:	54ffff3b 	bc\.lt	0 <\.text>  // bc\.tstop
+[^:]*:	54ffff1d 	bc\.le	0 <\.text>
+[^:]*:	54fffefc 	bc\.gt	0 <\.text>
+[^:]*:	54fffeda 	bc\.ge	0 <\.text>  // bc\.tcont
+[^:]*:	54fffeb3 	bc\.cc	0 <\.text>  // bc\.lo, bc\.ul, bc\.last
+[^:]*:	54fffe92 	bc\.cs	0 <\.text>  // bc\.hs, bc\.nlast
+[^:]*:	54fffe76 	bc\.vs	0 <\.text>
+[^:]*:	54fffe57 	bc\.vc	0 <\.text>
+[^:]*:	54fffe34 	bc\.mi	0 <\.text>  // bc\.first
+[^:]*:	54fffe15 	bc\.pl	0 <\.text>  // bc\.nfrst
+[^:]*:	54fffdf3 	bc\.cc	0 <\.text>  // bc\.lo, bc\.ul, bc\.last
+[^:]*:	54fffdd1 	bc\.ne	0 <\.text>  // bc\.any
+[^:]*:	54fffdb0 	bc\.eq	0 <\.text>  // bc\.none
+[^:]*:	54fffd94 	bc\.mi	0 <\.text>  // bc\.first
+[^:]*:	54fffd75 	bc\.pl	0 <\.text>  // bc\.nfrst
+[^:]*:	54fffd53 	bc\.cc	0 <\.text>  // bc\.lo, bc\.ul, bc\.last
+[^:]*:	54fffd32 	bc\.cs	0 <\.text>  // bc\.hs, bc\.nlast
+[^:]*:	54fffd18 	bc\.hi	0 <\.text>  // bc\.pmore
+[^:]*:	54fffcf9 	bc\.ls	0 <\.text>  // bc\.plast
+[^:]*:	54fffcda 	bc\.ge	0 <\.text>  // bc\.tcont
+[^:]*:	54fffcbb 	bc\.lt	0 <\.text>  // bc\.tstop
+[^:]*:	54fffc90 	bc\.eq	0 <\.text>  // bc\.none
diff --git a/gas/testsuite/gas/aarch64/hbc.s b/gas/testsuite/gas/aarch64/hbc.s
new file mode 100644
index 0000000..23af6ba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/hbc.s
@@ -0,0 +1,37 @@
+	.arch	armv8.8-a
+
+1:
+	bc.eq	1b
+	bc.ne	1b
+	bc.ls	1b
+	bc.lo	1b
+	bc.hi	1b
+	bc.hs	1b
+	bc.hi	1b
+	bc.lt	1b
+	bc.le	1b
+	bc.gt	1b
+	bc.ge	1b
+	bc.cc	1b
+	bc.cs	1b
+	bc.vs	1b
+	bc.vc	1b
+	bc.mi	1b
+	bc.pl	1b
+
+	bc.ul	1b
+
+	bc.any   1b
+	bc.none  1b
+	bc.first 1b
+	bc.nfrst 1b
+	bc.last  1b
+	bc.nlast 1b
+	bc.pmore 1b
+	bc.plast 1b
+	bc.tcont 1b
+	bc.tstop 1b
+
+	.arch	armv8.7-a+hbc
+
+	bc.eq	1b