* config/tc-ppc.c (parse_cpu): Preserve the settings of the

  PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.

* gas/ppc/altivec_and_spe.s: New test - checks that ISA extension
  command line options (-maltivec, -mspe) can be specified before
  CPU selection command line options.
* gas/ppc/altivec_and_spe.d: Expected disassembly.
* gas/ppc/ppc.exp: Run the new test

6 files changed, 40 insertions, 6 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7d7bb76..6fa4349 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2008-01-04  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-ppc.c (parse_cpu): Preserve the settings of the
+	PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.
+
 2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (md_assemble): Use !intel_mnemonic instead
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4ded149..8b3b2ee 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -825,6 +825,8 @@ const size_t md_longopts_size = sizeof (md_longopts);
 static int
 parse_cpu (const char *arg)
 {
+  unsigned long altivec_or_spe = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_SPE);
+
   /* -mpwrx and -mpwr2 mean to assemble for the IBM POWER/2
      (RIOS2).  */
   if (strcmp (arg, "pwrx") == 0 || strcmp (arg, "pwr2") == 0)
@@ -867,9 +869,9 @@ parse_cpu (const char *arg)
   else if (strcmp (arg, "altivec") == 0)
     {
       if (ppc_cpu == 0)
-	ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC;
-      else
-	ppc_cpu |= PPC_OPCODE_ALTIVEC;
+	ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC;
+
+      altivec_or_spe |= PPC_OPCODE_ALTIVEC;
     }
   else if (strcmp (arg, "e500") == 0 || strcmp (arg, "e500x2") == 0)
     {
@@ -881,9 +883,9 @@ parse_cpu (const char *arg)
   else if (strcmp (arg, "spe") == 0)
     {
       if (ppc_cpu == 0)
-	ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_SPE | PPC_OPCODE_EFS;
-      else
-	ppc_cpu |= PPC_OPCODE_SPE;
+	ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_EFS;
+
+      altivec_or_spe |= PPC_OPCODE_SPE;
     }
   /* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
      620.  */
@@ -941,6 +943,8 @@ parse_cpu (const char *arg)
   else
     return 0;
 
+  /* Make sure the the Altivec and SPE bits are not lost.  */
+  ppc_cpu |= altivec_or_spe;
   return 1;
 }
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 881f578..919a561 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2008-01-04  Nick Clifton  <nickc@redhat.com>
+
+	* gas/ppc/altivec_and_spe.s: New test - checks that ISA extension
+	command line options (-maltivec, -mspe) can be specified before
+	CPU selection command line options.
+	* gas/ppc/altivec_and_spe.d: Expected disassembly.
+	* gas/ppc/ppc.exp: Run the new test
+
 2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/arch-9.d: New file.
diff --git a/gas/testsuite/gas/ppc/altivec_and_spe.d b/gas/testsuite/gas/ppc/altivec_and_spe.d
new file mode 100644
index 0000000..f7b3356
--- /dev/null
+++ b/gas/testsuite/gas/ppc/altivec_and_spe.d
@@ -0,0 +1,12 @@
+#as: -maltivec -mspe -mppc64 
+#objdump: -d -Mppc64
+#name: Check that ISA extensions can be specified before CPU selection
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+   0:	7e 00 06 6c 	dssall
+   4:	7d 00 83 a6 	mtspr   512,r8
+   8:	4c 00 00 24 	rfid
diff --git a/gas/testsuite/gas/ppc/altivec_and_spe.s b/gas/testsuite/gas/ppc/altivec_and_spe.s
new file mode 100644
index 0000000..3328a41
--- /dev/null
+++ b/gas/testsuite/gas/ppc/altivec_and_spe.s
@@ -0,0 +1,4 @@
+	.text
+	dssall
+	mtspefscr 8
+	rfid
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 817f505..91870d4 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -39,6 +39,7 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "booke_xcoff64"
     } else {
 	run_dump_test "altivec"
+	run_dump_test "altivec_and_spe"
 	run_dump_test "booke"
 	run_dump_test "e500"
 	run_list_test "range" "-a32"