* gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.

	(do_crypto_3op_1): New function.
	(do_sha1c): Likewise.
	(do_sha1p): Likewise.
	(do_sha1m): Likewise.
	(do_sha1su0): Likewise.
	(do_sha256h): Likewise.
	(do_sha256h2): Likewise.
	(do_sha256su1): Likewise.
	(insns): Add SHA 3 operand instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.

5 files changed, 195 insertions, 2 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ff6ce6b..9253833 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,18 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+	* config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
+	(do_crypto_3op_1): New function.
+	(do_sha1c): Likewise.
+	(do_sha1p): Likewise.
+	(do_sha1m): Likewise.
+	(do_sha1su0): Likewise.
+	(do_sha256h): Likewise.
+	(do_sha256h2): Likewise.
+	(do_sha256su1): Likewise.
+	(insns): Add SHA 3 operand instructions.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
 	* config/tc-arm.c (neon_type_mask): Add P64 type.
 	(type_chk_of_el_type): Handle P64 type.
 	(el_type_of_type_chk): Likewise.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 627274c..b648bca 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12351,7 +12351,8 @@ struct neon_tab_entry
   X(vcvta,	0xebc0a40, 0x3bb0000, N_INV),		\
   X(vrintr,	0xeb60a40, 0x3ba0400, N_INV),		\
   X(vrinta,	0xeb80a40, 0x3ba0400, N_INV),		\
-  X(aes,	0x3b00300, N_INV,     N_INV)
+  X(aes,	0x3b00300, N_INV,     N_INV),		\
+  X(sha3op,	0x2000c00, N_INV,     N_INV)
 
 enum neon_opc
 {
@@ -16200,6 +16201,21 @@ do_crypto_2op_1 (unsigned elttype, int op)
 }
 
 static void
+do_crypto_3op_1 (int u, int op)
+{
+  set_it_insn_type (OUTSIDE_IT_INSN);
+
+  if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
+		       N_32 | N_UNT | N_KEY).type == NT_invtype)
+    return;
+
+  inst.error = NULL;
+
+  NEON_ENCODE (INTEGER, inst);
+  neon_three_same (1, u, 8 << op);
+}
+
+static void
 do_aese (void)
 {
   do_crypto_2op_1 (N_8, 0);
@@ -16223,7 +16239,47 @@ do_aesimc (void)
   do_crypto_2op_1 (N_8, 3);
 }
 
+static void
+do_sha1c (void)
+{
+  do_crypto_3op_1 (0, 0);
+}
+
+static void
+do_sha1p (void)
+{
+  do_crypto_3op_1 (0, 1);
+}
+
+static void
+do_sha1m (void)
+{
+  do_crypto_3op_1 (0, 2);
+}
+
+static void
+do_sha1su0 (void)
+{
+  do_crypto_3op_1 (0, 3);
+}
 
+static void
+do_sha256h (void)
+{
+  do_crypto_3op_1 (1, 0);
+}
+
+static void
+do_sha256h2 (void)
+{
+  do_crypto_3op_1 (1, 1);
+}
+
+static void
+do_sha256su1 (void)
+{
+  do_crypto_3op_1 (1, 2);
+}
 
 /* Overall per-instruction processing.	*/
 
@@ -18461,7 +18517,13 @@ static const struct asm_opcode insns[] =
   nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
   nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
   nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
-
+  nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
+  nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
+  nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
+  nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
+  nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
+  nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
+  nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3543cd7..06c8a8a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -5,6 +5,11 @@
 
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+	* gas/arm/armv8-a+crypto.d: Update testcase.
+	* gas/arm/armv8-a+crypto.s: Likewise.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
 	* gas/arm/armv8-a+crypto.d: New testcase.
 	* gas/arm/armv8-a+crypto.s: Likewise.
 
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index bfff964..f0ed1f4 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -22,6 +22,34 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3b0e3ce 	aesimc.8	q7, q7
 0[0-9a-f]+ <[^>]+> f3f003e0 	aesimc.8	q8, q8
 0[0-9a-f]+ <[^>]+> f3f0e3ee 	aesimc.8	q15, q15
+0[0-9a-f]+ <[^>]+> f2000c40 	sha1c.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f20eec4e 	sha1c.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2400ce0 	sha1c.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f24eecee 	sha1c.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2100c40 	sha1p.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f21eec4e 	sha1p.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2500ce0 	sha1p.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f25eecee 	sha1p.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2200c40 	sha1m.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f22eec4e 	sha1m.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2600ce0 	sha1m.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f26eecee 	sha1m.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2300c40 	sha1su0.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f23eec4e 	sha1su0.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2700ce0 	sha1su0.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f27eecee 	sha1su0.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3000c40 	sha256h.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f30eec4e 	sha256h.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3400ce0 	sha256h.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f34eecee 	sha256h.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3100c40 	sha256h2.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f31eec4e 	sha256h2.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3500ce0 	sha256h2.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f35eecee 	sha256h2.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200c40 	sha256su1.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f32eec4e 	sha256su1.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3600ce0 	sha256su1.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f36eecee 	sha256su1.32	q15, q15, q15
 0[0-9a-f]+ <[^>]+> efa0 0e00 	vmull.p64	q0, d0, d0
 0[0-9a-f]+ <[^>]+> efef eeaf 	vmull.p64	q15, d31, d31
 0[0-9a-f]+ <[^>]+> ffb0 0300 	aese.8	q0, q0
@@ -40,3 +68,31 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> ffb0 e3ce 	aesimc.8	q7, q7
 0[0-9a-f]+ <[^>]+> fff0 03e0 	aesimc.8	q8, q8
 0[0-9a-f]+ <[^>]+> fff0 e3ee 	aesimc.8	q15, q15
+0[0-9a-f]+ <[^>]+> ef00 0c40 	sha1c.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef0e ec4e 	sha1c.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef40 0ce0 	sha1c.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef4e ecee 	sha1c.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef10 0c40 	sha1p.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef1e ec4e 	sha1p.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef50 0ce0 	sha1p.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef5e ecee 	sha1p.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef20 0c40 	sha1m.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef2e ec4e 	sha1m.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef60 0ce0 	sha1m.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef6e ecee 	sha1m.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef30 0c40 	sha1su0.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef3e ec4e 	sha1su0.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef70 0ce0 	sha1su0.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef7e ecee 	sha1su0.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff00 0c40 	sha256h.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff0e ec4e 	sha256h.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff40 0ce0 	sha256h.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff4e ecee 	sha256h.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff10 0c40 	sha256h2.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff1e ec4e 	sha256h2.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff50 0ce0 	sha256h2.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff5e ecee 	sha256h2.32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0c40 	sha256su1.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff2e ec4e 	sha256su1.32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff60 0ce0 	sha256su1.32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff6e ecee 	sha256su1.32	q15, q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index 03b5c41..f6aac5a 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -21,6 +21,35 @@
 	aesimc.8	q7, q7
 	aesimc.8	q8, q8
 	aesimc.8	q15, q15
+	sha1c.32	q0, q0, q0
+	sha1c.32	q7, q7, q7
+	sha1c.32	q8, q8, q8
+	sha1c.32	q15, q15, q15
+	sha1p.32	q0, q0, q0
+	sha1p.32	q7, q7, q7
+	sha1p.32	q8, q8, q8
+	sha1p.32	q15, q15, q15
+	sha1m.32	q0, q0, q0
+	sha1m.32	q7, q7, q7
+	sha1m.32	q8, q8, q8
+	sha1m.32	q15, q15, q15
+	sha1su0.32	q0, q0, q0
+	sha1su0.32	q7, q7, q7
+	sha1su0.32	q8, q8, q8
+	sha1su0.32	q15, q15, q15
+	sha256h.32	q0, q0, q0
+	sha256h.32	q7, q7, q7
+	sha256h.32	q8, q8, q8
+	sha256h.32	q15, q15, q15
+	sha256h2.32	q0, q0, q0
+	sha256h2.32	q7, q7, q7
+	sha256h2.32	q8, q8, q8
+	sha256h2.32	q15, q15, q15
+	sha256su1.32	q0, q0, q0
+	sha256su1.32	q7, q7, q7
+	sha256su1.32	q8, q8, q8
+	sha256su1.32	q15, q15, q15
+
 
 	.thumb
 	vmull.p64	q0, d0, d0
@@ -41,3 +70,31 @@
 	aesimc.8	q7, q7
 	aesimc.8	q8, q8
 	aesimc.8	q15, q15
+	sha1c.32	q0, q0, q0
+	sha1c.32	q7, q7, q7
+	sha1c.32	q8, q8, q8
+	sha1c.32	q15, q15, q15
+	sha1p.32	q0, q0, q0
+	sha1p.32	q7, q7, q7
+	sha1p.32	q8, q8, q8
+	sha1p.32	q15, q15, q15
+	sha1m.32	q0, q0, q0
+	sha1m.32	q7, q7, q7
+	sha1m.32	q8, q8, q8
+	sha1m.32	q15, q15, q15
+	sha1su0.32	q0, q0, q0
+	sha1su0.32	q7, q7, q7
+	sha1su0.32	q8, q8, q8
+	sha1su0.32	q15, q15, q15
+	sha256h.32	q0, q0, q0
+	sha256h.32	q7, q7, q7
+	sha256h.32	q8, q8, q8
+	sha256h.32	q15, q15, q15
+	sha256h2.32	q0, q0, q0
+	sha256h2.32	q7, q7, q7
+	sha256h2.32	q8, q8, q8
+	sha256h2.32	q15, q15, q15
+	sha256su1.32	q0, q0, q0
+	sha256su1.32	q7, q7, q7
+	sha256su1.32	q8, q8, q8
+	sha256su1.32	q15, q15, q15