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author | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-04-28 18:21:00 -0700 |
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committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-05-06 06:43:32 -0700 |
commit | 41cee0897b670168e0d6f455c9bc45c73f8023df (patch) | |
tree | 90f15ebdf438ae1956dc5a3d7eea35c64ae41a10 /gas | |
parent | be0d3bbbcdbdba83f74d8ad1be6c4c759255af0b (diff) | |
download | fsf-binutils-gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.zip fsf-binutils-gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.tar.gz fsf-binutils-gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.tar.bz2 |
Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 12 | ||||
-rw-r--r-- | gas/config/tc-mips.c | 19 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/ase-errors-1.l | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/ase-errors-1.s | 12 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/eva.s | 13 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/mipsr6@eva.d | 32 |
6 files changed, 91 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index ec21153..e83a893 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,15 @@ +2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> + Faraz Shahbazker <fshahbazker@wavecomp.com> + + * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. + (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. + (mips_after_parse_args): Translate EVA to EVA_R6. + * testsuite/gas/mips/ase-errors-1.s: Add new instructions. + * testsuite/gas/mips/eva.s: Likewise. + * testsuite/gas/mips/ase-errors-1.l: Check errors for + new instructions. + * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. + 2019-05-06 Alan Modra <amodra@gmail.com> * symbols.c (symbol_relc_make_sym): Do not access sym->sy_value diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 091ea7b..6a945e3 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2227,7 +2227,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, /* Clear combination ASE flags, which need to be recalculated based on updated regular ASE settings. */ - opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT); + opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); if (enabled_p) opts->ase |= ase->flags; @@ -2246,6 +2246,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, mask |= ASE_MIPS16E2_MT; } + /* The EVA Extension has instructions which are only valid when the R6 ISA + is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are + present. */ + if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa)) + { + opts->ase |= ASE_EVA_R6; + mask |= ASE_EVA_R6; + } + return mask; } @@ -12017,6 +12026,7 @@ macro (struct mips_cl_insn *ip, char *str) goto ld; case M_LLDP_AB: case M_LLWP_AB: + case M_LLWPE_AB: s = ip->insn_mo->name; fmt = "t,d,s"; ll_sc_paired = 1; @@ -12125,6 +12135,7 @@ macro (struct mips_cl_insn *ip, char *str) goto ld_st; case M_SCDP_AB: case M_SCWP_AB: + case M_SCWPE_AB: s = ip->insn_mo->name; fmt = "t,d,s"; ll_sc_paired = 1; @@ -15246,6 +15257,12 @@ mips_after_parse_args (void) file_mips_opts.isa = arch_info->isa; file_mips_opts.init_ase = arch_info->ase; + /* The EVA Extension has instructions which are only valid when the R6 ISA + is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are + present. */ + if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa)) + file_mips_opts.ase |= ASE_EVA_R6; + /* Set up initial mips_opts state. */ mips_opts = file_mips_opts; diff --git a/gas/testsuite/gas/mips/ase-errors-1.l b/gas/testsuite/gas/mips/ase-errors-1.l index 2c9fb9e..b51db4f 100644 --- a/gas/testsuite/gas/mips/ase-errors-1.l +++ b/gas/testsuite/gas/mips/ase-errors-1.l @@ -48,3 +48,7 @@ .*:117: Warning: the `ginv' extension requires MIPS32 revision 6 or greater .*:120: Error: opcode not supported.* `ginvi \$a0' # ---------------------------------------------------------------------------- +.*:127: Error: opcode not supported .* `llwpe \$2,\$3,\$4' +.*:128: Error: opcode not supported .* `scwpe \$2,\$3,\$4' +.*:131: Error: opcode not supported .* `llwpe \$2,\$3,\$4' +.*:132: Error: opcode not supported .* `scwpe \$2,\$3,\$4' diff --git a/gas/testsuite/gas/mips/ase-errors-1.s b/gas/testsuite/gas/mips/ase-errors-1.s index 8b679a3..7deeea1 100644 --- a/gas/testsuite/gas/mips/ase-errors-1.s +++ b/gas/testsuite/gas/mips/ase-errors-1.s @@ -119,6 +119,18 @@ .set noginv ginvi $a0 # ERROR: ginv not enabled + .set mips32r6 + .set eva + llwpe $2, $3, $4 # OK + scwpe $2, $3, $4 # OK + .set noeva + llwpe $2, $3, $4 # ERROR: eva not enabled + scwpe $2, $3, $4 # ERROR: eva not enabled + .set mips32r5 + .set eva + llwpe $2, $3, $4 # ERROR: only avaialable on R6 + scwpe $2, $3, $4 # ERROR: only avaialable on R6 + # There should be no errors after this. .set fp=32 .set mips1 diff --git a/gas/testsuite/gas/mips/eva.s b/gas/testsuite/gas/mips/eva.s index 7865fb4..a8a7c05 100644 --- a/gas/testsuite/gas/mips/eva.s +++ b/gas/testsuite/gas/mips/eva.s @@ -615,3 +615,16 @@ test_eva: prefe 11,($12) prefe 13,MYDATA prefe 5,%lo(foo)($6) + + .ifdef r6 + llwpe $2, $3, 0x1234 + llwpe $2, $0, 0xabcd($0) + llwpe $0, $3, %lo(sync_mem) + llwpe $2, $2, 0xffffffff01234567($0) + llwpe $0, $0, sync_mem + scwpe $2, $3, 0x1234 + scwpe $2, $0, 0xabcd($0) + scwpe $0, $3, %lo(sync_mem) + scwpe $2, $2, 0xffffffff01234567($0) + scwpe $0, $0, sync_mem + .endif diff --git a/gas/testsuite/gas/mips/mipsr6@eva.d b/gas/testsuite/gas/mips/mipsr6@eva.d index 79b6030..4400f95 100644 --- a/gas/testsuite/gas/mips/mipsr6@eva.d +++ b/gas/testsuite/gas/mips/mipsr6@eva.d @@ -949,4 +949,36 @@ Disassembly of section \.text: [ 0-9a-f]+: 24c10000 addiu \$1,\$6,0 [ 0-9a-f]+: R_MIPS_LO16 foo [ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\) +[ 0-9a-f]+: 24021234 li \$2,4660 +[ 0-9a-f]+: 7c42186e llwpe \$2,\$3,\$2 +[ 0-9a-f]+: 3c020001 lui \$2,0x1 +[ 0-9a-f]+: 2442abcd addiu \$2,\$2,-21555 +[ 0-9a-f]+: 7c42006e llwpe \$2,\$0,\$2 +[ 0-9a-f]+: 24030000 li \$3,0 + [0-9a-f]+: R_MIPS_LO16 sync_mem +[ 0-9a-f]+: 7c60186e llwpe \$0,\$3,\$3 +[ 0-9a-f]+: 3c020123 lui \$2,0x123 +[ 0-9a-f]+: 24424567 addiu \$2,\$2,17767 +[ 0-9a-f]+: 7c42106e llwpe \$2,\$2,\$2 +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [0-9a-f]+: R_MIPS_HI16 sync_mem +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [0-9a-f]+: R_MIPS_LO16 sync_mem +[ 0-9a-f]+: 7c20006e llwpe \$0,\$0,\$1 +[ 0-9a-f]+: 24011234 li \$1,4660 +[ 0-9a-f]+: 7c22185e scwpe \$2,\$3,\$1 +[ 0-9a-f]+: 3c010001 lui \$1,0x1 +[ 0-9a-f]+: 2421abcd addiu \$1,\$1,-21555 +[ 0-9a-f]+: 7c22005e scwpe \$2,\$0,\$1 +[ 0-9a-f]+: 24010000 li \$1,0 + [0-9a-f]+: R_MIPS_LO16 sync_mem +[ 0-9a-f]+: 7c20185e scwpe \$0,\$3,\$1 +[ 0-9a-f]+: 3c010123 lui \$1,0x123 +[ 0-9a-f]+: 24214567 addiu \$1,\$1,17767 +[ 0-9a-f]+: 7c22105e scwpe \$2,\$2,\$1 +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [0-9a-f]+: R_MIPS_HI16 sync_mem +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [0-9a-f]+: R_MIPS_LO16 sync_mem +[ 0-9a-f]+: 7c20005e scwpe \$0,\$0,\$1 #pass |