RISC-V: Disassemble x0 based addresses as 0.

	gas/
	* testsuite/gas/riscv/auipc-x0.d: New.
	* testsuite/gas/riscv/auipc-x0.s: New.

	opcodes/
	* riscv-dis.c (maybe_print_address): If base_reg is zero,
	then the hi_addr value is zero.

3 files changed, 21 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 287656b..4ab6fa3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-09  Jim Wilson  <jimw@sifive.com>
+
+	* testsuite/gas/riscv/auipc-x0.d: New.
+	* testsuite/gas/riscv/auipc-x0.s: New.
+
 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 
 	* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
diff --git a/gas/testsuite/gas/riscv/auipc-x0.d b/gas/testsuite/gas/riscv/auipc-x0.d
new file mode 100644
index 0000000..bcf95af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/auipc-x0.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+#...
+[ 	]+40:[ 	]+00000017[ 	]+auipc[ 	]+zero,0x0
+[ 	]+44:[ 	]+00002003[ 	]+lw[ 	]+zero,0\(zero\) # 0 .*
diff --git a/gas/testsuite/gas/riscv/auipc-x0.s b/gas/testsuite/gas/riscv/auipc-x0.s
new file mode 100644
index 0000000..f7b394c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/auipc-x0.s
@@ -0,0 +1,4 @@
+target:
+	.skip 64
+	auipc x0, 0
+	lw x0, 0(x0)