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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-23 18:04:16 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-10-24 08:02:46 -0700 |
| commit | 3342be5dabeeaf2218dfbf4d38f92214612436f4 (patch) | |
| tree | e39053086e5e3873823abd2d77e630fc32926fe7 /gas | |
| parent | 3779bbe01b4ec1e5ae0a5c555f838999ba88ac50 (diff) | |
| download | fsf-binutils-gdb-3342be5dabeeaf2218dfbf4d38f92214612436f4.zip fsf-binutils-gdb-3342be5dabeeaf2218dfbf4d38f92214612436f4.tar.gz fsf-binutils-gdb-3342be5dabeeaf2218dfbf4d38f92214612436f4.tar.bz2 | |
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
This matches the ISA specification. This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.
bfd/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
when rd is x0.
include/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
immediate 0.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-lui-fail.d: New testcase.
gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
gas/testsuite/gas/riscv/riscv.exp: Likewise.
ld/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-lui-fail.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-lui-fail.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-lui-fail.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/riscv.exp | 1 |
5 files changed, 15 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7a9331d..a0f36f0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2017-10-24 Andrew Waterman <andrew@sifive.com> + + * testsuite/gas/riscv/c-lui-fail.d: New testcase. + gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. + gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. + gas/testsuite/gas/riscv/riscv.exp: Likewise. + 2017-10-24 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_pseudo_table): Add .code64 directive diff --git a/gas/testsuite/gas/riscv/c-lui-fail.d b/gas/testsuite/gas/riscv/c-lui-fail.d new file mode 100644 index 0000000..03e4596 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-lui-fail.s +#error-output: c-lui-fail.l diff --git a/gas/testsuite/gas/riscv/c-lui-fail.l b/gas/testsuite/gas/riscv/c-lui-fail.l new file mode 100644 index 0000000..5a4e990 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.lui x1,0' diff --git a/gas/testsuite/gas/riscv/c-lui-fail.s b/gas/testsuite/gas/riscv/c-lui-fail.s new file mode 100644 index 0000000..bb669bb --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.s @@ -0,0 +1,2 @@ +target: + c.lui x1, 0 diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp index 005238f..f411335 100644 --- a/gas/testsuite/gas/riscv/riscv.exp +++ b/gas/testsuite/gas/riscv/riscv.exp @@ -21,4 +21,5 @@ if [istarget riscv*-*-*] { run_dump_test "t_insns" run_dump_test "fmv.x" + run_dump_test "c-lui-fail" } |