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authorJan Beulich <jbeulich@suse.com>2019-12-04 10:43:50 +0100
committerJan Beulich <jbeulich@suse.com>2019-12-04 10:43:50 +0100
commit319ff62c8ab28c846365aef65c137735f8af88cb (patch)
tree1616b77f5058fa02f56b700e9a41064232cae358 /gas
parent77ad80922bf3042536fc41b19cc0bf230ea485b4 (diff)
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x86: consolidate tracking of MMX register use
Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead include the two special insns (not having register operands) explicitly.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-i386.c12
2 files changed, 8 insertions, 9 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b7d305f..dba3faa 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2019-12-04 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (output_insn): Don't consider Cpu* settings
+ when setting GNU_PROPERTY_X86_FEATURE_2_MMX.
+
+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
* testsuite/gas/i386/movdir.s: Add Intel syntax case with
operand size specifier.
* testsuite/gas/i386/x86-64-movdir.s: Add Intel syntax cases
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index b8babed..b62af34 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8259,15 +8259,9 @@ output_insn (void)
|| i.tm.cpu_flags.bitfield.cpu687
|| i.tm.cpu_flags.bitfield.cpufisttp)
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
- /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
- Xfence instructions. */
- if (i.tm.base_opcode != 0xf18
- && i.tm.base_opcode != 0xf0d
- && i.tm.base_opcode != 0xfaef8
- && (i.has_regmmx
- || i.tm.cpu_flags.bitfield.cpummx
- || i.tm.cpu_flags.bitfield.cpua3dnow
- || i.tm.cpu_flags.bitfield.cpua3dnowa))
+ if (i.has_regmmx
+ || i.tm.base_opcode == 0xf77 /* emms */
+ || i.tm.base_opcode == 0xf0e /* femms */)
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
if (i.has_regxmm)
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;