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| author | Nick Clifton <nickc@redhat.com> | 1998-12-21 12:42:28 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 1998-12-21 12:42:28 +0000 |
| commit | 29388c252046e7aefdae2e6d4cd1d8377f0fb000 (patch) | |
| tree | 08dd96d367fe02c8c37b3d2651b993868574c07a /gas | |
| parent | 6535b1df9239de0840ba3b05c11749a780a82399 (diff) | |
| download | fsf-binutils-gdb-29388c252046e7aefdae2e6d4cd1d8377f0fb000.zip fsf-binutils-gdb-29388c252046e7aefdae2e6d4cd1d8377f0fb000.tar.gz fsf-binutils-gdb-29388c252046e7aefdae2e6d4cd1d8377f0fb000.tar.bz2 | |
Fix for PR18233, emit a NOP after a relaxable 16 bit insn so that optimised
insns will start on a 32 bit boundary.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-m32r.c | 25 |
2 files changed, 29 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index cbfb4e1..24f8515 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +1998-12-21 Nick Clifton <nickc@cygnus.com> + + * config/tc-m32r.c (md_assemble): Emit a NOP after a relaxable 16 + bit insn when optimizing, so that parallelised instructions will + start on a 32 bit boundary. + 1998-12-19 Gavin Romig-Koch <gavin@cygnus.com> * config/tc-mips.c (mips_eabi64): New. diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c index 06146d4..35a04c3 100644 --- a/gas/config/tc-m32r.c +++ b/gas/config/tc-m32r.c @@ -731,6 +731,7 @@ target_make_parallel (buffer) /* Assemble two instructions with an explicit parallel operation (||) or sequential operation (->). */ + static void assemble_two_insns (str, str2, parallel_p) char * str; @@ -761,7 +762,14 @@ assemble_two_insns (str, str2, parallel_p) return; } - if (! enable_special + /* Check it. */ + if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) + { + /* xgettext:c-format */ + as_bad (_("not a 16 bit instruction '%s'"), str); + return; + } + else if (! enable_special && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL)) { /* xgettext:c-format */ @@ -838,7 +846,13 @@ assemble_two_insns (str, str2, parallel_p) } /* Check it. */ - if (! enable_special + if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) + { + /* xgettext:c-format */ + as_bad (_("not a 16 bit instruction '%s'"), str); + return; + } + else if (! enable_special && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL)) { /* xgettext:c-format */ @@ -1040,6 +1054,13 @@ md_assemble (str) insn.orig_insn = insn.insn; /* start-sanitize-m32rx */ + /* If the previous insn was relaxable, then it may be expanded + to fill the current 16 bit slot. Emit a NOP here to occupy + this slot, so that we can start at optimizing at a 32 bit + boundary. */ + if (prev_insn.insn && seen_relaxable_p && optimize) + fill_insn (0); + if (enable_m32rx) { /* Get the indices of the operands of the instruction. |