[ gas/ChangeLog ]

2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (mips_set_options): New "ase_mips3d" member.
	(mips_opts): Initialize "ase_mips3d" member.
	(file_ase_mips3d): New variable.
	(CPU_HAS_MIPS3D): New macro.
	(md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d
	based on command line options and configuration defaults.
	(macro_build, mips_ip): Accept MIPS-3D instructions if
	mips_opts.ase_mips3d is set.
	(OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option):
	Add support for "-mips3d" and "-no-mips3d" options.
	(OPTION_ELF_BASE): Move to accomodate new options.
	(s_mipsset): Support ".set mips3d" and ".set nomips3d".
	(mips_elf_final_processing): Add a comment indicating that a
	MIPS-3D ASE ELF header flag should be set, when one exists.
	* doc/as.texinfo: Document -mips3d and -no-mips3d options.
	* doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set
	nomips3d" directives.

[ gas/testsuite/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* gas/mips/mips64-mips3d.s: New file.
	* gas/mips/mips64-mips3d.d: Likewise.
	* gas/mips/mips.exp: Run new "mips64-mips3d" test.

[ include/opcode/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
	instructions.
	(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
	may be passed along with the ISA bitmask.

[ opcodes/ChangeLog ]
2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
	bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64.  Add
	comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
	indicate that they should dissassemble all applicable
	MIPS-specified ASEs.
	* mips-opc.c: Add support for MIPS-3D instructions.
	(M3D): New definition.

	* mips-opc.c: Update copyright years.

8 files changed, 392 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d69da3c..526a64e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,23 @@
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.c (mips_set_options): New "ase_mips3d" member.
+	(mips_opts): Initialize "ase_mips3d" member.
+	(file_ase_mips3d): New variable.
+	(CPU_HAS_MIPS3D): New macro.
+	(md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d
+	based on command line options and configuration defaults.
+	(macro_build, mips_ip): Accept MIPS-3D instructions if
+	mips_opts.ase_mips3d is set.
+	(OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option):
+	Add support for "-mips3d" and "-no-mips3d" options.
+	(OPTION_ELF_BASE): Move to accomodate new options.
+	(s_mipsset): Support ".set mips3d" and ".set nomips3d".
+	(mips_elf_final_processing): Add a comment indicating that a
+	MIPS-3D ASE ELF header flag should be set, when one exists.
+	* doc/as.texinfo: Document -mips3d and -no-mips3d options.
+	* doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set
+	nomips3d" directives.
+	
 2002-03-14  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	* config/tc-mmix.c (md_estimate_size_before_relax): Don't consider
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index b3acb5c..54d24be 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -137,6 +137,10 @@ struct mips_set_options
      if it has not been initialized.  Changed by `.set mipsN', and the
      -mipsN command line option, and the default CPU.  */
   int isa;
+  /* Enabled Application Specific Extensions (ASEs).  These are set to -1
+     if they have not been initialized.  Changed by `.set <asename>', by
+     command line options, and based on the default architecture.  */
+  int ase_mips3d;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
      Changed by `.set mips16' and `.set nomips16', and the -mips16 and
@@ -185,7 +189,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
+  ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -197,6 +201,10 @@ unsigned long mips_cprmask[4];
 /* MIPS ISA we are using for this output file.  */
 static int file_mips_isa = ISA_UNKNOWN;
 
+/* True if -mips3d was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_mips3d;
+
 /* The argument of the -mcpu= flag.  Historical for code generation.  */
 static int mips_cpu = CPU_UNKNOWN;
 
@@ -263,6 +271,10 @@ static int mips_32bitmode = 0;
 
 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
 
+/* Return true if the given CPU supports the MIPS3D ASE.  */
+#define CPU_HAS_MIPS3D(cpu)	((cpu) == CPU_SB1      \
+				 )
+
 /* Whether the processor uses hardware interlocks to protect
    reads from the HI and LO registers, and thus does not
    require nops to be inserted.  */
@@ -1223,6 +1235,11 @@ md_begin ()
       && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
     mips_32bitmode = 1;
 
+  /* If the selected architecture includes support for ASEs, enable
+     generation of code for them.  */
+  if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
+    mips_opts.ase_mips3d = 1;
+
   if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
     as_warn (_("Could not set architecture and machine"));
 
@@ -1233,6 +1250,7 @@ md_begin ()
 
   file_mips_isa = mips_opts.isa;
   file_mips_abi = mips_opts.abi;
+  file_ase_mips3d = mips_opts.ase_mips3d;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
 
@@ -2885,7 +2903,10 @@ macro_build (place, counter, ep, name, fmt, va_alist)
     {
       if (strcmp (fmt, insn.insn_mo->args) == 0
 	  && insn.insn_mo->pinfo != INSN_MACRO
-	  && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
+	  && OPCODE_IS_MEMBER (insn.insn_mo,
+			       (mips_opts.isa
+	      		        | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
+			       mips_arch)
 	  && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
 	break;
 
@@ -7670,7 +7691,10 @@ mips_ip (str, ip)
 
       assert (strcmp (insn->name, str) == 0);
 
-      if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch))
+      if (OPCODE_IS_MEMBER (insn,
+			    (mips_opts.isa
+	      		     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
+			    mips_arch))
 	ok = true;
       else
 	ok = false;
@@ -9738,8 +9762,12 @@ struct option md_longopts[] =
   {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
 #define OPTION_GP64 (OPTION_MD_BASE + 32)
   {"mgp64", no_argument, NULL, OPTION_GP64},
+#define OPTION_MIPS3D (OPTION_MD_BASE + 33)
+  {"mips3d", no_argument, NULL, OPTION_MIPS3D},
+#define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
+  {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
 #ifdef OBJ_ELF
-#define OPTION_ELF_BASE    (OPTION_MD_BASE + 33)
+#define OPTION_ELF_BASE    (OPTION_MD_BASE + 35)
 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
   {"KPIC",        no_argument, NULL, OPTION_CALL_SHARED},
   {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
@@ -9954,6 +9982,14 @@ md_parse_option (c, arg)
       mips_no_prev_insn (false);
       break;
 
+    case OPTION_MIPS3D:
+      mips_opts.ase_mips3d = 1;
+      break;
+
+    case OPTION_NO_MIPS3D:
+      mips_opts.ase_mips3d = 0;
+      break;
+
     case OPTION_MEMBEDDED_PIC:
       mips_pic = EMBEDDED_PIC;
       if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
@@ -11275,6 +11311,10 @@ s_mipsset (x)
   else if (strcmp (name, "nomips16") == 0
 	   || strcmp (name, "noMIPS-16") == 0)
     mips_opts.mips16 = 0;
+  else if (strcmp (name, "mips3d") == 0)
+    mips_opts.ase_mips3d = 1;
+  else if (strcmp (name, "nomips3d") == 0)
+    mips_opts.ase_mips3d = 0;
   else if (strncmp (name, "mips", 4) == 0)
     {
       int isa;
@@ -12763,6 +12803,12 @@ mips_elf_final_processing ()
   if (mips_pic != NO_PIC)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
 
+  /* Set MIPS ELF flags for ASEs. */
+#if 0 /* XXX FIXME */
+  if (file_ase_mips3d)
+    elf_elfheader (stdoutput)->e_flags |= ???;
+#endif
+
   /* Set the MIPS ELF ABI flags.  */
   if (file_mips_abi == NO_ABI)
     ;
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index b6c14fa..2a1d05e 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -374,6 +374,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}]
    [@b{-mips32}] [@b{-mips64}]
    [@b{-m4650}] [@b{-no-m4650}]
+   [@b{-mips3d}] [@b{-no-mips3d}]
    [@b{--trap}] [@b{--break}] [@b{-n}]
    [@b{--emulation}=@var{name} ]
 @end ifset
@@ -881,6 +882,12 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
 instructions around accesses to the @samp{HI} and @samp{LO} registers.
 @samp{-no-m4650} turns off this option.
 
+@item -mips3d
+@itemx -no-mips3d
+Generate code for the MIPS-3D Application Specific Extension.
+This tells the assembler to accept MIPS-3D instructions.
+@samp{-no-mips3d} turns off this option.
+
 @item -mcpu=@var{CPU}
 Generate code for a particular MIPS cpu.  It is exactly equivalent to
 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index a114fee..1fbe180 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -97,6 +97,12 @@ Generate code for the MIPS 16 processor.  This is equivalent to putting
 @samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -mips3d
+@itemx -no-mips3d
+Generate code for the MIPS-3D Application Specific Extension.
+This tells the assembler to accept MIPS-3D instructions.
+@samp{-no-mips3d} turns off this option.
+
 @item -mfix7000
 @itemx -no-mfix7000
 Cause nops to be inserted if the read of the destination register
@@ -323,3 +329,16 @@ option such as the ISA level or instruction reordering but does not want
 to change the state of the code which invoked the macro.
 
 Traditional @sc{mips} assemblers do not support these directives.
+
+@node MIPS ASE instruction generation overrides
+@section Directives to control generation of MIPS ASE instructions
+
+@cindex MIPS MIPS-3D instruction generation override
+@kindex @code{.set mips3d}
+@kindex @code{.set nomips3d}
+The directive @code{.set mips3d} makes the assembler accept instructions
+from the MIPS-3D Application Specific Extension from that point on
+in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
+instructions from being accepted.
+
+Traditional @sc{mips} assemblers do not support these directives.
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e496fd6..332d820 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,11 @@
 2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
 
+	* gas/mips/mips64-mips3d.s: New file.
+	* gas/mips/mips64-mips3d.d: Likewise.
+	* gas/mips/mips.exp: Run new "mips64-mips3d" test.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
 	* gas/mips/mips.exp: Use elf-rel2 and elfel-rel2 for
 	mipsisa32*-*-* targets, rather than e32-rel2 and e32el-rel2.
 
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 8ffc370..c57341f 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -142,6 +142,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "sync"
     run_dump_test "mips32"
     run_dump_test "mips64"
+    run_dump_test "mips64-mips3d"
     run_dump_test "sb1-ext-ps"
 
     # It will always fail until someone fixes it.
diff --git a/gas/testsuite/gas/mips/mips64-mips3d.d b/gas/testsuite/gas/mips/mips64-mips3d.d
new file mode 100644
index 0000000..7b8f06a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-mips3d.d
@@ -0,0 +1,138 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64
+#name: MIPS MIPS64 MIPS-3D ASE instructions
+#as: -mips64 -mips3d
+
+# Check MIPS64 MIPS-3D ASE instruction assembly and disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46d34118 	addr\.ps	\$f4,\$f8,\$f19
+0+0004 <[^>]*> 4520fffe 	bc1any2f	\$fcc0,0+0000 <text_label>
+0+0008 <[^>]*> 00000000 	nop
+0+000c <[^>]*> 4528fffc 	bc1any2f	\$fcc2,0+0000 <text_label>
+0+0010 <[^>]*> 00000000 	nop
+0+0014 <[^>]*> 4521fffa 	bc1any2t	\$fcc0,0+0000 <text_label>
+0+0018 <[^>]*> 00000000 	nop
+0+001c <[^>]*> 4531fff8 	bc1any2t	\$fcc4,0+0000 <text_label>
+0+0020 <[^>]*> 00000000 	nop
+0+0024 <[^>]*> 4540fff6 	bc1any4f	\$fcc0,0+0000 <text_label>
+0+0028 <[^>]*> 00000000 	nop
+0+002c <[^>]*> 4550fff4 	bc1any4f	\$fcc4,0+0000 <text_label>
+0+0030 <[^>]*> 00000000 	nop
+0+0034 <[^>]*> 4541fff2 	bc1any4t	\$fcc0,0+0000 <text_label>
+0+0038 <[^>]*> 00000000 	nop
+0+003c <[^>]*> 4551fff0 	bc1any4t	\$fcc4,0+0000 <text_label>
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 46334070 	cabs\.f\.d	\$fcc0,\$f8,\$f19
+0+0048 <[^>]*> 46334270 	cabs\.f\.d	\$fcc2,\$f8,\$f19
+0+004c <[^>]*> 46134070 	cabs\.f\.s	\$fcc0,\$f8,\$f19
+0+0050 <[^>]*> 46134270 	cabs\.f\.s	\$fcc2,\$f8,\$f19
+0+0054 <[^>]*> 46d34070 	cabs\.f\.ps	\$fcc0,\$f8,\$f19
+0+0058 <[^>]*> 46d34270 	cabs\.f\.ps	\$fcc2,\$f8,\$f19
+0+005c <[^>]*> 46334071 	cabs\.un\.d	\$fcc0,\$f8,\$f19
+0+0060 <[^>]*> 46334271 	cabs\.un\.d	\$fcc2,\$f8,\$f19
+0+0064 <[^>]*> 46134071 	cabs\.un\.s	\$fcc0,\$f8,\$f19
+0+0068 <[^>]*> 46134271 	cabs\.un\.s	\$fcc2,\$f8,\$f19
+0+006c <[^>]*> 46d34071 	cabs\.un\.ps	\$fcc0,\$f8,\$f19
+0+0070 <[^>]*> 46d34271 	cabs\.un\.ps	\$fcc2,\$f8,\$f19
+0+0074 <[^>]*> 46334072 	cabs\.eq\.d	\$fcc0,\$f8,\$f19
+0+0078 <[^>]*> 46334272 	cabs\.eq\.d	\$fcc2,\$f8,\$f19
+0+007c <[^>]*> 46134072 	cabs\.eq\.s	\$fcc0,\$f8,\$f19
+0+0080 <[^>]*> 46134272 	cabs\.eq\.s	\$fcc2,\$f8,\$f19
+0+0084 <[^>]*> 46d34072 	cabs\.eq\.ps	\$fcc0,\$f8,\$f19
+0+0088 <[^>]*> 46d34272 	cabs\.eq\.ps	\$fcc2,\$f8,\$f19
+0+008c <[^>]*> 46334073 	cabs\.ueq\.d	\$fcc0,\$f8,\$f19
+0+0090 <[^>]*> 46334273 	cabs\.ueq\.d	\$fcc2,\$f8,\$f19
+0+0094 <[^>]*> 46134073 	cabs\.ueq\.s	\$fcc0,\$f8,\$f19
+0+0098 <[^>]*> 46134273 	cabs\.ueq\.s	\$fcc2,\$f8,\$f19
+0+009c <[^>]*> 46d34073 	cabs\.ueq\.ps	\$fcc0,\$f8,\$f19
+0+00a0 <[^>]*> 46d34273 	cabs\.ueq\.ps	\$fcc2,\$f8,\$f19
+0+00a4 <[^>]*> 46334074 	cabs\.olt\.d	\$fcc0,\$f8,\$f19
+0+00a8 <[^>]*> 46334274 	cabs\.olt\.d	\$fcc2,\$f8,\$f19
+0+00ac <[^>]*> 46134074 	cabs\.olt\.s	\$fcc0,\$f8,\$f19
+0+00b0 <[^>]*> 46134274 	cabs\.olt\.s	\$fcc2,\$f8,\$f19
+0+00b4 <[^>]*> 46d34074 	cabs\.olt\.ps	\$fcc0,\$f8,\$f19
+0+00b8 <[^>]*> 46d34274 	cabs\.olt\.ps	\$fcc2,\$f8,\$f19
+0+00bc <[^>]*> 46334075 	cabs\.ult\.d	\$fcc0,\$f8,\$f19
+0+00c0 <[^>]*> 46334275 	cabs\.ult\.d	\$fcc2,\$f8,\$f19
+0+00c4 <[^>]*> 46134075 	cabs\.ult\.s	\$fcc0,\$f8,\$f19
+0+00c8 <[^>]*> 46134275 	cabs\.ult\.s	\$fcc2,\$f8,\$f19
+0+00cc <[^>]*> 46d34075 	cabs\.ult\.ps	\$fcc0,\$f8,\$f19
+0+00d0 <[^>]*> 46d34275 	cabs\.ult\.ps	\$fcc2,\$f8,\$f19
+0+00d4 <[^>]*> 46334076 	cabs\.ole\.d	\$fcc0,\$f8,\$f19
+0+00d8 <[^>]*> 46334276 	cabs\.ole\.d	\$fcc2,\$f8,\$f19
+0+00dc <[^>]*> 46134076 	cabs\.ole\.s	\$fcc0,\$f8,\$f19
+0+00e0 <[^>]*> 46134276 	cabs\.ole\.s	\$fcc2,\$f8,\$f19
+0+00e4 <[^>]*> 46d34076 	cabs\.ole\.ps	\$fcc0,\$f8,\$f19
+0+00e8 <[^>]*> 46d34276 	cabs\.ole\.ps	\$fcc2,\$f8,\$f19
+0+00ec <[^>]*> 46334077 	cabs\.ule\.d	\$fcc0,\$f8,\$f19
+0+00f0 <[^>]*> 46334277 	cabs\.ule\.d	\$fcc2,\$f8,\$f19
+0+00f4 <[^>]*> 46134077 	cabs\.ule\.s	\$fcc0,\$f8,\$f19
+0+00f8 <[^>]*> 46134277 	cabs\.ule\.s	\$fcc2,\$f8,\$f19
+0+00fc <[^>]*> 46d34077 	cabs\.ule\.ps	\$fcc0,\$f8,\$f19
+0+0100 <[^>]*> 46d34277 	cabs\.ule\.ps	\$fcc2,\$f8,\$f19
+0+0104 <[^>]*> 46334078 	cabs\.sf\.d	\$fcc0,\$f8,\$f19
+0+0108 <[^>]*> 46334278 	cabs\.sf\.d	\$fcc2,\$f8,\$f19
+0+010c <[^>]*> 46134078 	cabs\.sf\.s	\$fcc0,\$f8,\$f19
+0+0110 <[^>]*> 46134278 	cabs\.sf\.s	\$fcc2,\$f8,\$f19
+0+0114 <[^>]*> 46d34078 	cabs\.sf\.ps	\$fcc0,\$f8,\$f19
+0+0118 <[^>]*> 46d34278 	cabs\.sf\.ps	\$fcc2,\$f8,\$f19
+0+011c <[^>]*> 46334079 	cabs\.ngle\.d	\$fcc0,\$f8,\$f19
+0+0120 <[^>]*> 46334279 	cabs\.ngle\.d	\$fcc2,\$f8,\$f19
+0+0124 <[^>]*> 46134079 	cabs\.ngle\.s	\$fcc0,\$f8,\$f19
+0+0128 <[^>]*> 46134279 	cabs\.ngle\.s	\$fcc2,\$f8,\$f19
+0+012c <[^>]*> 46d34079 	cabs\.ngle\.ps	\$fcc0,\$f8,\$f19
+0+0130 <[^>]*> 46d34279 	cabs\.ngle\.ps	\$fcc2,\$f8,\$f19
+0+0134 <[^>]*> 4633407a 	cabs\.seq\.d	\$fcc0,\$f8,\$f19
+0+0138 <[^>]*> 4633427a 	cabs\.seq\.d	\$fcc2,\$f8,\$f19
+0+013c <[^>]*> 4613407a 	cabs\.seq\.s	\$fcc0,\$f8,\$f19
+0+0140 <[^>]*> 4613427a 	cabs\.seq\.s	\$fcc2,\$f8,\$f19
+0+0144 <[^>]*> 46d3407a 	cabs\.seq\.ps	\$fcc0,\$f8,\$f19
+0+0148 <[^>]*> 46d3427a 	cabs\.seq\.ps	\$fcc2,\$f8,\$f19
+0+014c <[^>]*> 4633407b 	cabs\.ngl\.d	\$fcc0,\$f8,\$f19
+0+0150 <[^>]*> 4633427b 	cabs\.ngl\.d	\$fcc2,\$f8,\$f19
+0+0154 <[^>]*> 4613407b 	cabs\.ngl\.s	\$fcc0,\$f8,\$f19
+0+0158 <[^>]*> 4613427b 	cabs\.ngl\.s	\$fcc2,\$f8,\$f19
+0+015c <[^>]*> 46d3407b 	cabs\.ngl\.ps	\$fcc0,\$f8,\$f19
+0+0160 <[^>]*> 46d3427b 	cabs\.ngl\.ps	\$fcc2,\$f8,\$f19
+0+0164 <[^>]*> 4633407c 	cabs\.lt\.d	\$fcc0,\$f8,\$f19
+0+0168 <[^>]*> 4633427c 	cabs\.lt\.d	\$fcc2,\$f8,\$f19
+0+016c <[^>]*> 4613407c 	cabs\.lt\.s	\$fcc0,\$f8,\$f19
+0+0170 <[^>]*> 4613427c 	cabs\.lt\.s	\$fcc2,\$f8,\$f19
+0+0174 <[^>]*> 46d3407c 	cabs\.lt\.ps	\$fcc0,\$f8,\$f19
+0+0178 <[^>]*> 46d3427c 	cabs\.lt\.ps	\$fcc2,\$f8,\$f19
+0+017c <[^>]*> 4633407d 	cabs\.nge\.d	\$fcc0,\$f8,\$f19
+0+0180 <[^>]*> 4633427d 	cabs\.nge\.d	\$fcc2,\$f8,\$f19
+0+0184 <[^>]*> 4613407d 	cabs\.nge\.s	\$fcc0,\$f8,\$f19
+0+0188 <[^>]*> 4613427d 	cabs\.nge\.s	\$fcc2,\$f8,\$f19
+0+018c <[^>]*> 46d3407d 	cabs\.nge\.ps	\$fcc0,\$f8,\$f19
+0+0190 <[^>]*> 46d3427d 	cabs\.nge\.ps	\$fcc2,\$f8,\$f19
+0+0194 <[^>]*> 4633407e 	cabs\.le\.d	\$fcc0,\$f8,\$f19
+0+0198 <[^>]*> 4633427e 	cabs\.le\.d	\$fcc2,\$f8,\$f19
+0+019c <[^>]*> 4613407e 	cabs\.le\.s	\$fcc0,\$f8,\$f19
+0+01a0 <[^>]*> 4613427e 	cabs\.le\.s	\$fcc2,\$f8,\$f19
+0+01a4 <[^>]*> 46d3407e 	cabs\.le\.ps	\$fcc0,\$f8,\$f19
+0+01a8 <[^>]*> 46d3427e 	cabs\.le\.ps	\$fcc2,\$f8,\$f19
+0+01ac <[^>]*> 4633407f 	cabs\.ngt\.d	\$fcc0,\$f8,\$f19
+0+01b0 <[^>]*> 4633427f 	cabs\.ngt\.d	\$fcc2,\$f8,\$f19
+0+01b4 <[^>]*> 4613407f 	cabs\.ngt\.s	\$fcc0,\$f8,\$f19
+0+01b8 <[^>]*> 4613427f 	cabs\.ngt\.s	\$fcc2,\$f8,\$f19
+0+01bc <[^>]*> 46d3407f 	cabs\.ngt\.ps	\$fcc0,\$f8,\$f19
+0+01c0 <[^>]*> 46d3427f 	cabs\.ngt\.ps	\$fcc2,\$f8,\$f19
+0+01c4 <[^>]*> 46c09924 	cvt\.pw\.ps	\$f4,\$f19
+0+01c8 <[^>]*> 46809926 	cvt\.ps\.pw	\$f4,\$f19
+0+01cc <[^>]*> 46d3411a 	mulr\.ps	\$f4,\$f8,\$f19
+0+01d0 <[^>]*> 46209a1d 	recip1\.d	\$f8,\$f19
+0+01d4 <[^>]*> 46009a1d 	recip1\.s	\$f8,\$f19
+0+01d8 <[^>]*> 46c09a1d 	recip1\.ps	\$f8,\$f19
+0+01dc <[^>]*> 4633411c 	recip2\.d	\$f4,\$f8,\$f19
+0+01e0 <[^>]*> 4613411c 	recip2\.s	\$f4,\$f8,\$f19
+0+01e4 <[^>]*> 46d3411c 	recip2\.ps	\$f4,\$f8,\$f19
+0+01e8 <[^>]*> 46209a1e 	rsqrt1\.d	\$f8,\$f19
+0+01ec <[^>]*> 46009a1e 	rsqrt1\.s	\$f8,\$f19
+0+01f0 <[^>]*> 46c09a1e 	rsqrt1\.ps	\$f8,\$f19
+0+01f4 <[^>]*> 4633411f 	rsqrt2\.d	\$f4,\$f8,\$f19
+0+01f8 <[^>]*> 4613411f 	rsqrt2\.s	\$f4,\$f8,\$f19
+0+01fc <[^>]*> 46d3411f 	rsqrt2\.ps	\$f4,\$f8,\$f19
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips64-mips3d.s b/gas/testsuite/gas/mips/mips64-mips3d.s
new file mode 100644
index 0000000..5c5e8a8
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-mips3d.s
@@ -0,0 +1,151 @@
+# source file to test assembly of mips64 MIPS-3D ASE instructions
+
+	.set noreorder
+	.set noat
+
+	.globl text_label .text
+text_label:
+
+	addr.ps		$f4, $f8, $f19
+
+	bc1any2f	$fcc0, text_label
+	nop
+	bc1any2f	$fcc2, text_label
+	nop
+
+	bc1any2t	$fcc0, text_label
+	nop
+	bc1any2t	$fcc4, text_label
+	nop
+
+	bc1any4f	$fcc0, text_label
+	nop
+	bc1any4f	$fcc4, text_label
+	nop
+
+	bc1any4t	$fcc0, text_label
+	nop
+	bc1any4t	$fcc4, text_label
+	nop
+
+	cabs.f.d	$fcc0, $f8, $f19
+	cabs.f.d	$fcc2, $f8, $f19
+	cabs.f.s	$fcc0, $f8, $f19
+	cabs.f.s	$fcc2, $f8, $f19
+	cabs.f.ps	$fcc0, $f8, $f19
+	cabs.f.ps	$fcc2, $f8, $f19
+	cabs.un.d	$fcc0, $f8, $f19
+	cabs.un.d	$fcc2, $f8, $f19
+	cabs.un.s	$fcc0, $f8, $f19
+	cabs.un.s	$fcc2, $f8, $f19
+	cabs.un.ps	$fcc0, $f8, $f19
+	cabs.un.ps	$fcc2, $f8, $f19
+	cabs.eq.d	$fcc0, $f8, $f19
+	cabs.eq.d	$fcc2, $f8, $f19
+	cabs.eq.s	$fcc0, $f8, $f19
+	cabs.eq.s	$fcc2, $f8, $f19
+	cabs.eq.ps	$fcc0, $f8, $f19
+	cabs.eq.ps	$fcc2, $f8, $f19
+	cabs.ueq.d	$fcc0, $f8, $f19
+	cabs.ueq.d	$fcc2, $f8, $f19
+	cabs.ueq.s	$fcc0, $f8, $f19
+	cabs.ueq.s	$fcc2, $f8, $f19
+	cabs.ueq.ps	$fcc0, $f8, $f19
+	cabs.ueq.ps	$fcc2, $f8, $f19
+	cabs.olt.d	$fcc0, $f8, $f19
+	cabs.olt.d	$fcc2, $f8, $f19
+	cabs.olt.s	$fcc0, $f8, $f19
+	cabs.olt.s	$fcc2, $f8, $f19
+	cabs.olt.ps	$fcc0, $f8, $f19
+	cabs.olt.ps	$fcc2, $f8, $f19
+	cabs.ult.d	$fcc0, $f8, $f19
+	cabs.ult.d	$fcc2, $f8, $f19
+	cabs.ult.s	$fcc0, $f8, $f19
+	cabs.ult.s	$fcc2, $f8, $f19
+	cabs.ult.ps	$fcc0, $f8, $f19
+	cabs.ult.ps	$fcc2, $f8, $f19
+	cabs.ole.d	$fcc0, $f8, $f19
+	cabs.ole.d	$fcc2, $f8, $f19
+	cabs.ole.s	$fcc0, $f8, $f19
+	cabs.ole.s	$fcc2, $f8, $f19
+	cabs.ole.ps	$fcc0, $f8, $f19
+	cabs.ole.ps	$fcc2, $f8, $f19
+	cabs.ule.d	$fcc0, $f8, $f19
+	cabs.ule.d	$fcc2, $f8, $f19
+	cabs.ule.s	$fcc0, $f8, $f19
+	cabs.ule.s	$fcc2, $f8, $f19
+	cabs.ule.ps	$fcc0, $f8, $f19
+	cabs.ule.ps	$fcc2, $f8, $f19
+	cabs.sf.d	$fcc0, $f8, $f19
+	cabs.sf.d	$fcc2, $f8, $f19
+	cabs.sf.s	$fcc0, $f8, $f19
+	cabs.sf.s	$fcc2, $f8, $f19
+	cabs.sf.ps	$fcc0, $f8, $f19
+	cabs.sf.ps	$fcc2, $f8, $f19
+	cabs.ngle.d	$fcc0, $f8, $f19
+	cabs.ngle.d	$fcc2, $f8, $f19
+	cabs.ngle.s	$fcc0, $f8, $f19
+	cabs.ngle.s	$fcc2, $f8, $f19
+	cabs.ngle.ps	$fcc0, $f8, $f19
+	cabs.ngle.ps	$fcc2, $f8, $f19
+	cabs.seq.d	$fcc0, $f8, $f19
+	cabs.seq.d	$fcc2, $f8, $f19
+	cabs.seq.s	$fcc0, $f8, $f19
+	cabs.seq.s	$fcc2, $f8, $f19
+	cabs.seq.ps	$fcc0, $f8, $f19
+	cabs.seq.ps	$fcc2, $f8, $f19
+	cabs.ngl.d	$fcc0, $f8, $f19
+	cabs.ngl.d	$fcc2, $f8, $f19
+	cabs.ngl.s	$fcc0, $f8, $f19
+	cabs.ngl.s	$fcc2, $f8, $f19
+	cabs.ngl.ps	$fcc0, $f8, $f19
+	cabs.ngl.ps	$fcc2, $f8, $f19
+	cabs.lt.d	$fcc0, $f8, $f19
+	cabs.lt.d	$fcc2, $f8, $f19
+	cabs.lt.s	$fcc0, $f8, $f19
+	cabs.lt.s	$fcc2, $f8, $f19
+	cabs.lt.ps	$fcc0, $f8, $f19
+	cabs.lt.ps	$fcc2, $f8, $f19
+	cabs.nge.d	$fcc0, $f8, $f19
+	cabs.nge.d	$fcc2, $f8, $f19
+	cabs.nge.s	$fcc0, $f8, $f19
+	cabs.nge.s	$fcc2, $f8, $f19
+	cabs.nge.ps	$fcc0, $f8, $f19
+	cabs.nge.ps	$fcc2, $f8, $f19
+	cabs.le.d	$fcc0, $f8, $f19
+	cabs.le.d	$fcc2, $f8, $f19
+	cabs.le.s	$fcc0, $f8, $f19
+	cabs.le.s	$fcc2, $f8, $f19
+	cabs.le.ps	$fcc0, $f8, $f19
+	cabs.le.ps	$fcc2, $f8, $f19
+	cabs.ngt.d	$fcc0, $f8, $f19
+	cabs.ngt.d	$fcc2, $f8, $f19
+	cabs.ngt.s	$fcc0, $f8, $f19
+	cabs.ngt.s	$fcc2, $f8, $f19
+	cabs.ngt.ps	$fcc0, $f8, $f19
+	cabs.ngt.ps	$fcc2, $f8, $f19
+
+	cvt.pw.ps	$f4, $f19
+
+	cvt.ps.pw	$f4, $f19
+
+	mulr.ps		$f4, $f8, $f19
+
+	recip1.d	$f8, $f19
+	recip1.s	$f8, $f19
+	recip1.ps	$f8, $f19
+
+	recip2.d	$f4, $f8, $f19
+	recip2.s	$f4, $f8, $f19
+	recip2.ps	$f4, $f8, $f19
+
+	rsqrt1.d	$f8, $f19
+	rsqrt1.s	$f8, $f19
+	rsqrt1.ps	$f8, $f19
+
+	rsqrt2.d	$f4, $f8, $f19
+	rsqrt2.s	$f4, $f8, $f19
+	rsqrt2.ps	$f4, $f8, $f19
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8