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| author | Michael Eager <eager@eagercon.com> | 2012-11-21 17:34:14 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2012-11-21 17:34:14 +0000 |
| commit | 0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc (patch) | |
| tree | ebab98525dfab07eff0f4c02b90b40d3770ca3ee /gas | |
| parent | e0f33b1fbf3b88882abd0d4136b8d1307e351c9d (diff) | |
| download | fsf-binutils-gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.zip fsf-binutils-gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.tar.gz fsf-binutils-gdb-0db4b3260cfc1818dba17ee53bb8e6ca6fdefecc.tar.bz2 | |
Add stack high register and stack low register for MicroBlaze
hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
binutils/opcodes
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/config/tc-microblaze.c | 20 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/microblaze/allinsn.d | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/microblaze/allinsn.s | 10 |
5 files changed, 49 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index c9c0e36..184d306 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com> + + * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR + 2012-11-20 H.J. Lu <hongjiu.lu@intel.com> PR gas/14859 diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c index b71383b..5a427a0 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c @@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg) } return s; } + /* Stack protection registers. */ + else if (strncasecmp (s, "rshr", 4) == 0) + { + *reg = REG_SHR; + return s + 4; + } + else if (strncasecmp (s, "rslr", 4) == 0) + { + *reg = REG_SLR; + return s + 4; + } else { if (TOLOWER (s[0]) == 'r') @@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg) || (*reg == REG_PID) || (*reg == REG_ZPR) || (*reg == REG_TLBX) || (*reg == REG_TLBLO) || (*reg == REG_TLBHI) || (*reg == REG_TLBSX) + || (*reg == REG_SHR) || (*reg == REG_SLR) || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM)) return TRUE; @@ -1280,6 +1292,10 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_TLBLO_MASK; else if (reg2 == REG_TLBHI) immed = opcode->immval_mask | REG_TLBHI_MASK; + else if (reg2 == REG_SHR) + immed = opcode->immval_mask | REG_SHR_MASK; + else if (reg2 == REG_SLR) + immed = opcode->immval_mask | REG_SLR_MASK; else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM)) immed = opcode->immval_mask | REG_PVR_MASK | reg2; else @@ -1331,6 +1347,10 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_TLBHI_MASK; else if (reg1 == REG_TLBSX) immed = opcode->immval_mask | REG_TLBSX_MASK; + else if (reg1 == REG_SHR) + immed = opcode->immval_mask | REG_SHR_MASK; + else if (reg1 == REG_SLR) + immed = opcode->immval_mask | REG_SLR_MASK; else as_fatal (_("invalid value for special purpose register")); inst |= (reg2 << RA_LOW) & RA_MASK; diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index b05f281..f460b47 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-11-21 David Holsgrove <david.holsgrove@xilinx.com> + + * gas/microblaze/allinsn.s: Test use of SHR, SLR + * gas/microblaze/allinsn.d: Likewise + 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z9-109.d: Fix srstu opcode. diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d index ec14020..4a03340 100644 --- a/gas/testsuite/gas/microblaze/allinsn.d +++ b/gas/testsuite/gas/microblaze/allinsn.d @@ -31,3 +31,13 @@ Disassembly of section .text: 00000020 <sleep>: 20: ba020004 sleep + +00000024 <regslr>: + 24: b0000000 imm 0 + 28: 31600000 addik r11, r0, 0 + 2c: 940bc800 mts rslr, r11 + +00000030 <regshr>: + 30: b0000000 imm 0 + 34: 31600000 addik r11, r0, 0 + 38: 940bc802 mts rshr, r11 diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s index 582da17..437444f 100644 --- a/gas/testsuite/gas/microblaze/allinsn.s +++ b/gas/testsuite/gas/microblaze/allinsn.s @@ -36,4 +36,14 @@ mbar: .global sleep sleep: sleep + .text + .global regslr +regslr: + la r11,r0,r0 + mts rslr,r11 + .text + .global regshr +regshr: + la r11,r0,r0 + mts rshr,r11 |