diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2020-02-16 08:36:51 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-02-16 08:45:34 -0800 |
| commit | af5c13b01ecc416d26321a2d60943d787ba24c7f (patch) | |
| tree | b0e6fc6295a084b1c2a14340722b09300fe8ea35 /gas | |
| parent | 5de9bb826dd155601da1e5e34060a1e7e443eee8 (diff) | |
| download | fsf-binutils-gdb-af5c13b01ecc416d26321a2d60943d787ba24c7f.zip fsf-binutils-gdb-af5c13b01ecc416d26321a2d60943d787ba24c7f.tar.gz fsf-binutils-gdb-af5c13b01ecc416d26321a2d60943d787ba24c7f.tar.bz2 | |
x86: Don't disable SSE4a when disabling SSE4
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel
SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also
adds .sse4a and nosse4a.
gas/
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 5 | ||||
| -rw-r--r-- | gas/doc/c-i386.texi | 4 |
3 files changed, 13 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index e30c0dd..a148526 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-02-16 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore + nosse4. + * doc/c-i386.texi: Document sse4a and nosse4a. + 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> * doc/c-i386.texi: Remove the old movsx and movzx documentation diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 9e59eca..6cc7696 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -983,6 +983,8 @@ static const arch_entry cpu_arch[] = CPU_SSE2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, CPU_SSE3_FLAGS, 0 }, + { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, + CPU_SSE4A_FLAGS, 0 }, { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, CPU_SSSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, @@ -1177,10 +1179,11 @@ static const noarch_entry cpu_noarch[] = { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, + { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, - { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_FLAGS }, + { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 235a395..91586cd 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -151,6 +151,7 @@ accept various extension mnemonics. For example, @code{sse}, @code{sse2}, @code{sse3}, +@code{sse4a}, @code{ssse3}, @code{sse4.1}, @code{sse4.2}, @@ -158,6 +159,7 @@ accept various extension mnemonics. For example, @code{nosse}, @code{nosse2}, @code{nosse3}, +@code{nosse4a}, @code{nossse3}, @code{nosse4.1}, @code{nosse4.2}, @@ -1428,7 +1430,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} -@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @samp{.sse4a} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} |