Add binutils support for v850e1 processor

8 files changed, 133 insertions, 3 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index aee80e5..c1c79db 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2003-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-v850.c (set_machine): Accept v850e1 machine number.
+	(md_pseudo_table): Add .v850e1 pseudo op.
+	(md_show_usage): Document -mv850e1 switch.
+	(md_parse_option): Accept -mv850e1 switch.
+	(md_begin): Allow TARGET_CPU to be v850e1.
+	* doc/c-v850.texi: Document -mv850e1 switch and .v850e1 pseudo op.
+	* NEWS: Mention support for v850e1.
+
 2003-09-04  Alan Modra  <amodra@bigpond.net.au>
 
 	* config/tc-ppc.c (md_parse_option): Add PPC_OPCODE_ANY to existing
diff --git a/gas/NEWS b/gas/NEWS
index 3393d9c..b1c5b31 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Added support for v850e1.
+
 * Added -n switch for x86 assembler.  By default, x86 GAS replaces
   multiple nop instructions used for alignment within code sections
   with multi-byte nop instructions such as leal 0(%esi,1),%esi.  This
diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index 1e618aa..25fea3a 100644
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -479,6 +479,7 @@ set_machine (number)
     {
     case 0:		  processor_mask = PROCESSOR_V850;   break;
     case bfd_mach_v850e:  processor_mask = PROCESSOR_V850E;  break;
+    case bfd_mach_v850e1: processor_mask = PROCESSOR_V850E;  break;
     }
 }
 
@@ -539,6 +540,7 @@ const pseudo_typeS md_pseudo_table[] =
   { "call_table_data",	v850_seg,		CALL_TABLE_DATA_SECTION	},
   { "call_table_text",	v850_seg,		CALL_TABLE_TEXT_SECTION	},
   { "v850e",		set_machine,		bfd_mach_v850e		},
+  { "v850e1",		set_machine,		bfd_mach_v850e1 	},
   { "longcall",		v850_longcode,		1			},
   { "longjump",		v850_longcode,		2			},
   { NULL,		NULL,			0			}
@@ -1156,6 +1158,7 @@ md_show_usage (stream)
   fprintf (stream, _("  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"));
   fprintf (stream, _("  -mv850                    The code is targeted at the v850\n"));
   fprintf (stream, _("  -mv850e                   The code is targeted at the v850e\n"));
+  fprintf (stream, _("  -mv850e1                  The code is targeted at the v850e1\n"));
   fprintf (stream, _("  -mv850any                 The code is generic, despite any processor specific instructions\n"));
   fprintf (stream, _("  -mrelax                   Enable relaxation\n"));
 }
@@ -1191,6 +1194,11 @@ md_parse_option (c, arg)
       machine = bfd_mach_v850e;
       processor_mask = PROCESSOR_V850E;
     }
+  else if (strcmp (arg, "v850e1") == 0)
+    {
+      machine = bfd_mach_v850e1;
+      processor_mask = PROCESSOR_V850E1;
+    }
   else if (strcmp (arg, "v850any") == 0)
     {
       /* Tell the world that this is for any v850 chip.  */
@@ -1198,6 +1206,7 @@ md_parse_option (c, arg)
 
       /* But support instructions for the extended versions.  */
       processor_mask = PROCESSOR_V850E;
+      processor_mask |= PROCESSOR_V850E1;
     }
   else if (strcmp (arg, "relax") == 0)
     v850_relax = 1;
@@ -1327,7 +1336,15 @@ md_begin ()
   char *prev_name = "";
   const struct v850_opcode *op;
 
-  if (strncmp (TARGET_CPU, "v850e", 5) == 0)
+  if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
+    {
+      if (machine == -1)
+	machine = bfd_mach_v850e1;
+
+      if (processor_mask == -1)
+	processor_mask = PROCESSOR_V850E1;
+    }
+  else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
     {
       if (machine == -1)
 	machine = bfd_mach_v850e;
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 432f3ba..5fd4bac 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -1,4 +1,4 @@
-@c Copyright 1997 Free Software Foundation, Inc.
+@c Copyright 1997, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -51,6 +51,12 @@ Specifies that the assembled code should be marked as being targeted at
 the V850E processor.  This allows the linker to detect attempts to link
 such code with code assembled for other processors.
 
+@cindex @code{-mv850e1} command line option, V850
+@item -mv850e1
+Specifies that the assembled code should be marked as being targeted at
+the V850E1 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
 @cindex @code{-mv850any} command line option, V850
 @item -mv850any
 Specifies that the assembled code should be marked as being targeted at
@@ -233,6 +239,12 @@ Specifies that the assembled code should be marked as being targeted at
 the V850E processor.  This allows the linker to detect attempts to link
 such code with code assembled for other processors.
 
+@cindex @code{.v850e1} directive, V850
+@item .v850e1
+Specifies that the assembled code should be marked as being targeted at
+the V850E1 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
 @end table
 
 @node V850 Opcodes
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 454488d..54324dd 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* gas/v850/v850e1.s: New test source file.
+	* gas/v850/v850e1.d: New test disassembly file.
+	* gas/v850/basic.exp: Run v850e1 test.
+
 2003-09-03  Robert Millan  <robertmh@gnu.org>
 
 	* gas/alpha/alpha.exp: Match GNU/KFreeBSD with new kfreebsd*-gnu
diff --git a/gas/testsuite/gas/v850/basic.exp b/gas/testsuite/gas/v850/basic.exp
index 9943813..e3b0713 100644
--- a/gas/testsuite/gas/v850/basic.exp
+++ b/gas/testsuite/gas/v850/basic.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1996 Free Software Foundation, Inc.
+# Copyright (C) 1996, 2003 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -435,4 +435,5 @@ if [istarget v850*-*-*] then {
     gas_test "fepsw.s" "" "" "eqsw regression test"
 
     gas_test_error "range.s" "-mwarn-signed-overflow" "Check for range error on byte load/store"
+    run_dump_test "v850e1"
 }
diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d
new file mode 100644
index 0000000..9fb689b
--- /dev/null
+++ b/gas/testsuite/gas/v850/v850e1.d
@@ -0,0 +1,44 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: V850E1 instruction tests
+#as: -mv850e1
+
+# Test the new instructions in the V850E1 processor
+
+.*: +file format .*v850.*
+
+Disassembly of section .text:
+0x0+00 e0 0f 42 13 [ 	]*bsh	r1, r2
+0x0+04 e0 1f 40 23 [ 	]*bsw	sp, gp
+0x0+08 05 02  [ 	]*callt	5
+0x0+0a e8 3f e4 00 [ 	]*clr1	r7, r8
+0x0+0e f6 17 14 1b [ 	]*cmov	nz, -10, r2, sp
+0x0+12 e1 17 34 1b [ 	]*cmov	nz, r1, r2, sp
+0x0+16 e0 07 44 01 [ 	]*ctret	
+0x0+1a e0 07 46 01 [ 	]*dbret	
+0x0+1e 40 f8  [ 	]*dbtrap	
+0x0+20 4e 06 00 80 [ 	]*dispose	7, {r24}, r0
+0x0+24 4e 06 05 70 [ 	]*dispose	7, {r25 - r27}, r5
+0x0+28 e1 17 c0 1a [ 	]*div	r1, r2, sp
+0x0+2c e4 2f 80 32 [ 	]*divh	gp, r5, r6
+0x0+30 e7 47 82 4a [ 	]*divhu	r7, r8, r9
+0x0+34 ea 5f c2 62 [ 	]*divu	r10, r11, r12
+0x0+38 e0 6f 44 73 [ 	]*hsw	r13, r14
+0x0+3c a1 17 0d 00 [ 	]*ld.bu	13\[r1\],r2
+0x0+40 e3 27 11 00 [ 	]*ld.hu	16\[sp\],gp
+0x0+44 21 06 78 56 34 12 [ 	]*mov	0x12345678, r1
+0x0+4a e5 17 40 1a [ 	]*mul	5, r2, sp
+0x0+4e e1 17 20 1a [ 	]*mul	r1, r2, sp
+0x0+52 e4 2f 22 32 [ 	]*mulu	gp, r5, r6
+0x0+56 e3 2f 46 32 [ 	]*mulu	35, r5, r6
+0x0+5a ea 4f e2 00 [ 	]*not1	r9, r10
+0x0+5e a8 07 01 80 [ 	]*prepare	{r24}, 20
+0x0+62 a8 07 03 70 [ 	]*prepare	{r25 - r27}, 20, sp
+0x0+66 e1 4f e0 00 [ 	]*set1	r9, r1
+0x0+6a ea 47 00 02 [ 	]*sasf	nz, r8
+0x0+6e 60 20  [ 	]*sld.bu	0\[ep\],gp
+0x0+70 77 28  [ 	]*sld.hu	14\[ep\],r5
+0x0+72 a1 00  [ 	]*sxb	r1
+0x0+74 e2 00  [ 	]*sxh	r2
+0x0+76 ff 07 e6 00 [ 	]*tst1	r0, lp
+0x0+7a 83 00  [ 	]*zxb	sp
+0x0+7c c4 00  [ 	]*zxh	gp
diff --git a/gas/testsuite/gas/v850/v850e1.s b/gas/testsuite/gas/v850/v850e1.s
new file mode 100644
index 0000000..5013261
--- /dev/null
+++ b/gas/testsuite/gas/v850/v850e1.s
@@ -0,0 +1,38 @@
+.text
+.align 0
+	
+	bsh	r1, r2
+	bsw	r3, r4
+	callt	5
+	clr1	r7, [r8]
+	cmov	nz, 22, r2, r3
+	cmov	nz, r1, r2, r3
+	ctret	
+	dbret
+	dbtrap		
+	dispose	7, {r24}
+	dispose	7, {r25 - r27}, r5
+	div	r1, r2, r3
+	divh	r4, r5, r6
+	divhu	r7, r8, r9
+	divu	r10, r11, r12
+	hsw	r13, r14
+	ld.bu	13 [r1], r2
+	ld.hu	16 [r3], r4
+	mov	0x12345678, r1
+	mul	5, r2, r3
+	mul	r1, r2, r3
+	mulu	r4, r5, r6
+	mulu	35, r5, r6
+	not1	r9, [r10]
+	prepare	{r24}, 20
+	prepare	{r25 - r27}, 20, sp
+	set1	r9, [r1]
+	sasf	nz, r8
+	sld.bu	0 [ep], r4
+	sld.hu	14 [ep], r5
+	sxb	r1
+	sxh	r2
+	tst1	r0, [r31]
+	zxb	r3
+	zxh	r4