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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:46:21 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:46:21 +0000 |
| commit | 4fd0a9fd005ea3affe8e61f6ec82817055a3bc2b (patch) | |
| tree | 5bf37bc494996c35fe21429720bdce25e01cc00d /gas | |
| parent | b5b0f34c669a91b9d873221ea3d688cf7f495ab5 (diff) | |
| download | fsf-binutils-gdb-4fd0a9fd005ea3affe8e61f6ec82817055a3bc2b.zip fsf-binutils-gdb-4fd0a9fd005ea3affe8e61f6ec82817055a3bc2b.tar.gz fsf-binutils-gdb-4fd0a9fd005ea3affe8e61f6ec82817055a3bc2b.tar.bz2 | |
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.s | 14 |
3 files changed, 36 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 62a7030..2259d86 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,6 +1,12 @@ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. + * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift + by immediate instructions. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d index a6792ee..b29c9da 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.d +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d @@ -547,3 +547,19 @@ Disassembly of section \.text: [0-9a-f]+: 6f1dfc41 fcvtzu v1.8h, v2.8h, #3 [0-9a-f]+: 2f1ffc00 fcvtzu v0.4h, v0.4h, #1 [0-9a-f]+: 6f1ffc00 fcvtzu v0.8h, v0.8h, #1 + [0-9a-f]+: 5f7de441 scvtf d1, d2, #3 + [0-9a-f]+: 5f3de441 scvtf s1, s2, #3 + [0-9a-f]+: 5f1de441 scvtf h1, h2, #3 + [0-9a-f]+: 5f1fe400 scvtf h0, h0, #1 + [0-9a-f]+: 5f7dfc41 fcvtzs d1, d2, #3 + [0-9a-f]+: 5f3dfc41 fcvtzs s1, s2, #3 + [0-9a-f]+: 5f1dfc41 fcvtzs h1, h2, #3 + [0-9a-f]+: 5f1ffc00 fcvtzs h0, h0, #1 + [0-9a-f]+: 7f7de441 ucvtf d1, d2, #3 + [0-9a-f]+: 7f3de441 ucvtf s1, s2, #3 + [0-9a-f]+: 7f1de441 ucvtf h1, h2, #3 + [0-9a-f]+: 7f1fe400 ucvtf h0, h0, #1 + [0-9a-f]+: 7f7dfc41 fcvtzu d1, d2, #3 + [0-9a-f]+: 7f3dfc41 fcvtzu s1, s2, #3 + [0-9a-f]+: 7f1dfc41 fcvtzu h1, h2, #3 + [0-9a-f]+: 7f1ffc00 fcvtzu h0, h0, #1 diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s index 1eb7418..8be4854 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.s +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s @@ -244,3 +244,17 @@ shift_imm fcvtzs shift_imm ucvtf shift_imm fcvtzu + + /* Adv.SIMD scalar shift by immediate. */ + + .macro sshift_imm, op + \op d1, d2, #3 + \op s1, s2, #3 + \op h1, h2, #3 + \op h0, h0, #1 + .endm + + sshift_imm scvtf + sshift_imm fcvtzs + sshift_imm ucvtf + sshift_imm fcvtzu |