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authorH.J. Lu <hjl.tools@gmail.com>2020-02-17 07:12:10 -0800
committerH.J. Lu <hjl.tools@gmail.com>2020-02-17 07:31:28 -0800
commit272a84b1204fdd4e96df689383b163b4a52be933 (patch)
tree9f293c0d74a1424fe7386f2ad175e4e4874b968d /gas
parent1f730c46141c1513e72cb24d471834b448d6d0e6 (diff)
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x86: Remove CpuABM and add CpuPOPCNT
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt which used to be the part of SSE4.2. This patch removes CpuABM and adds CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2 to also enable popcnt. gas/ * config/tc-i386.c (cpu_arch): Add .popcnt. * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. Add a tab before @samp{.sse4a}. opcodes/ * i386-gen.c (cpu_flag_init): Replace CpuABM with CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add CPU_POPCNT_FLAGS. (cpu_flags): Remove CpuABM. Add CpuPOPCNT. * i386-opc.h (CpuABM): Removed. (CpuPOPCNT): New. (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on popcnt. Remove CpuABM from lzcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-i386.c2
-rw-r--r--gas/doc/c-i386.texi11
3 files changed, 14 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b6ce3ef..095e457 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .popcnt.
+ * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
+ Add a tab before @samp{.sse4a}.
+
2020-02-17 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Don't try to guess a suffix
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c4c94ca..f559ad4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1055,6 +1055,8 @@ static const arch_entry cpu_arch[] =
CPU_EPT_FLAGS, 0 },
{ STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
CPU_LZCNT_FLAGS, 0 },
+ { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN,
+ CPU_POPCNT_FLAGS, 0 },
{ STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
CPU_HLE_FLAGS, 0 },
{ STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 91586cd..8c8e8d0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -238,6 +238,7 @@ accept various extension mnemonics. For example,
@code{movbe},
@code{ept},
@code{lzcnt},
+@code{popcnt},
@code{hle},
@code{rtm},
@code{invpcid},
@@ -260,8 +261,7 @@ accept various extension mnemonics. For example,
@code{3dnowa},
@code{sse4a},
@code{sse5},
-@code{svme},
-@code{abm} and
+@code{svme} and
@code{padlock}.
Note that rather than extending a basic instruction set, the extension
mnemonics starting with @code{no} revoke the respective functionality.
@@ -1430,13 +1430,14 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
-@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @samp{.sse4a}
+@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
-@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
+@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
+@item @samp{.hle}
@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
@@ -1450,7 +1451,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
-@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
+@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
@item @samp{.mcommit}