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| author | Borislav Petkov <bp@suse.de> | 2017-07-05 11:27:49 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-07-05 11:27:49 +0200 |
| commit | e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2 (patch) | |
| tree | 9659a1146cb84fda14a65d62524d3d85e65c03b1 /gas/testsuite | |
| parent | 60c96dbf02fcdb30942b9db7a138afcfc2b7220e (diff) | |
| download | fsf-binutils-gdb-e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2.zip fsf-binutils-gdb-e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2.tar.gz fsf-binutils-gdb-e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2.tar.bz2 | |
X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/i386/opcode.d | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/opcode.s | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-opcode.d | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-opcode.s | 9 |
4 files changed, 30 insertions, 0 deletions
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d index c7dc410..b80a78c 100644 --- a/gas/testsuite/gas/i386/opcode.d +++ b/gas/testsuite/gas/i386/opcode.d @@ -603,4 +603,10 @@ Disassembly of section .text: +[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl +[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx +[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx + +[a-f0-9]+: c0 f0 02 shl \$0x2,%al + +[a-f0-9]+: c1 f0 01 shl \$0x1,%eax + +[a-f0-9]+: d0 f0 shl %al + +[a-f0-9]+: d1 f0 shl %eax + +[a-f0-9]+: d2 f0 shl %cl,%al + +[a-f0-9]+: d3 f0 shl %cl,%eax #pass diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s index 64357b5..db47446 100644 --- a/gas/testsuite/gas/i386/opcode.s +++ b/gas/testsuite/gas/i386/opcode.s @@ -604,3 +604,9 @@ foo: .byte 0xf6, 0xc9, 0x01 .byte 0x66, 0xf7, 0xc9, 0x02, 0x00 .byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00 + .byte 0xc0, 0xf0, 0x02 + .byte 0xc1, 0xf0, 0x01 + .byte 0xd0, 0xf0 + .byte 0xd1, 0xf0 + .byte 0xd2, 0xf0 + .byte 0xd3, 0xf0 diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d index a6087e0..bfffb6e 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.d +++ b/gas/testsuite/gas/i386/x86-64-opcode.d @@ -305,4 +305,13 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx [ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx [ ]*[a-f0-9]+: 48 f7 c9 08 00 00 00 test \$(0x)?0*8,%rcx +[ ]*[a-f0-9]+: c0 f0 02 shl \$0x2,%al +[ ]*[a-f0-9]+: c1 f0 01 shl \$0x1,%eax +[ ]*[a-f0-9]+: 48 c1 f0 01 shl \$0x1,%rax +[ ]*[a-f0-9]+: d0 f0 shl %al +[ ]*[a-f0-9]+: d1 f0 shl %eax +[ ]*[a-f0-9]+: 48 d1 f0 shl %rax +[ ]*[a-f0-9]+: d2 f0 shl %cl,%al +[ ]*[a-f0-9]+: d3 f0 shl %cl,%eax +[ ]*[a-f0-9]+: 48 d3 f0 shl %cl,%rax #pass diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s index ffc8b94..5df5d13 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.s +++ b/gas/testsuite/gas/i386/x86-64-opcode.s @@ -432,3 +432,12 @@ .byte 0x66, 0xf7, 0xc9, 0x02, 0x00 .byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00 .byte 0x48, 0xf7, 0xc9, 0x08, 0x00, 0x00, 0x00 + .byte 0xc0, 0xf0, 0x02 + .byte 0xc1, 0xf0, 0x01 + .byte 0x48, 0xc1, 0xf0, 0x01 + .byte 0xd0, 0xf0 + .byte 0xd1, 0xf0 + .byte 0x48, 0xd1, 0xf0 + .byte 0xd2, 0xf0 + .byte 0xd3, 0xf0 + .byte 0x48, 0xd3, 0xf0 |