[AArch64] Add missing C_MAX_ELEM flags for SVE conversions

SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.

Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.

gas/
	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
	SCVTF, UCVTF, LSR and ASR.
	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.

3 files changed, 73 insertions, 7 deletions

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.d b/gas/testsuite/gas/aarch64/sve-movprfx_26.d
index 00bafdc..1f7a85d 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.d
@@ -16,8 +16,48 @@ Disassembly of section .*:
 [^:]+:	65cba440 	fcvt	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
 [^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
 [^:]+:	65cba440 	fcvt	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d8a440 	fcvtzs	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d8a440 	fcvtzs	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65dca440 	fcvtzs	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65dca440 	fcvtzs	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d9a440 	fcvtzu	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d9a440 	fcvtzu	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65dda440 	fcvtzu	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65dda440 	fcvtzu	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d4a440 	scvtf	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d4a440 	scvtf	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d0a440 	scvtf	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d0a440 	scvtf	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d5a440 	ucvtf	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d5a440 	ucvtf	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d1a440 	ucvtf	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d1a440 	ucvtf	z0.d, p1/m, z2.s
 [^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
 [^:]+:	041b8440 	lsl	z0.b, p1/m, z0.b, z2.d
 [^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
 [^:]+:	041b8440 	lsl	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
+[^:]+:	04198440 	lsr	z0.b, p1/m, z0.b, z2.d
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	04198440 	lsr	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
+[^:]+:	04188440 	asr	z0.b, p1/m, z0.b, z2.d
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	04188440 	asr	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
 [^:]+:	d65f03c0 	ret
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.l b/gas/testsuite/gas/aarch64/sve-movprfx_26.l
index 695f90f..3595566 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.l
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.l
@@ -1,4 +1,14 @@
 [^:]*: Assembler messages:
 .*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.S,P1/M,Z2.D'
 .*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.D,P1/M,Z2.S'
-.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
\ No newline at end of file
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsr Z0.B,P1/M,Z0.B,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `asr Z0.B,P1/M,Z0.B,Z2.D'
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.s b/gas/testsuite/gas/aarch64/sve-movprfx_26.s
index 15f52db..859a0e2 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.s
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.s
@@ -4,28 +4,44 @@
   .arch armv8-a+sve
 
 f:
+  .macro test_cvt, insn
+
   /* Not OK, 64-bit operation, upper 32-bits cleared.  */
   movprfx Z0.S, P1/M, Z1.S
-  fcvt Z0.S, P1/M, Z2.D
+  \insn Z0.S, P1/M, Z2.D
 
   /* OK, 64-bit operation, upper 32-bits cleared.  */
   movprfx Z0.D, P1/M, Z1.D
-  fcvt Z0.S, P1/M, Z2.D
+  \insn Z0.S, P1/M, Z2.D
 
   /* Not OK, 64-bit operation ignoring 32-bits.  */
   movprfx Z0.S, P1/M, Z1.S
-  fcvt Z0.D, P1/M, Z2.S
+  \insn Z0.D, P1/M, Z2.S
 
   /* OK, 64-bit operation ignoring 32-bits.  */
   movprfx Z0.D, P1/M, Z1.D
-  fcvt Z0.D, P1/M, Z2.S
+  \insn Z0.D, P1/M, Z2.S
+  .endm test_cvt
 
+  .macro test_shift, insn
   /* OK, 8-bit operation.  */
   movprfx Z0.B, P1/M, Z1.B
-  lsl Z0.B, P1/M, Z0.B, Z2.D
+  \insn Z0.B, P1/M, Z0.B, Z2.D
 
   /* Not Ok, destination register sizes don't match.  */
   movprfx Z0.D, P1/M, Z1.D
-  lsl Z0.B, P1/M, Z0.B, Z2.D
+  \insn Z0.B, P1/M, Z0.B, Z2.D
+  .endm test_shift
+
+  test_cvt fcvt
+  test_cvt fcvtzs
+  test_cvt fcvtzu
+  test_cvt scvtf
+  test_cvt ucvtf
+
+  test_shift lsl
+  test_shift lsr
+  test_shift asr
+
   ret