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authorRichard Sandiford <richard.sandiford@arm.com>2019-07-02 10:52:16 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2019-07-02 10:52:16 +0100
commit01c1ee4a70478178eb37e46692a02fb846a2f77b (patch)
tree1c8b12ac321f90dc418b83cb26dca8ed7ec33e19 /gas/testsuite
parent83adff695c522df8259e421162e194a95713eb45 (diff)
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[AArch64] Allow MOVPRFX to be used with FMOV
The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX. (The entry for FCPY itself was OK.) This was the only /m-predicated instruction I could see that was missing the flag. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the SVE FMOV alias of FCPY. gas/ * testsuite/gas/aarch64/sve-movprfx_27.s, * testsuite/gas/aarch64/sve-movprfx_27.d: New test.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/gas/aarch64/sve-movprfx_27.d14
-rw-r--r--gas/testsuite/gas/aarch64/sve-movprfx_27.s11
2 files changed, 25 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_27.d b/gas/testsuite/gas/aarch64/sve-movprfx_27.d
new file mode 100644
index 0000000..ef0bc9a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_27.d
@@ -0,0 +1,14 @@
+#source: sve-movprfx_27.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 0420bc20 movprfx z0, z1
+[^:]+: 0590ce00 fmov z0.s, p0/m, #1.0+(e\+00)?
+[^:]+: 0420bc20 movprfx z0, z1
+[^:]+: 0590ce00 fmov z0.s, p0/m, #1.0+(e\+00)?
+[^:]+: d65f03c0 ret
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_27.s b/gas/testsuite/gas/aarch64/sve-movprfx_27.s
new file mode 100644
index 0000000..bb4d3a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_27.s
@@ -0,0 +1,11 @@
+ .text
+ .arch armv8-a+sve
+
+f:
+ movprfx z0, z1
+ fmov z0.s, p0/m, #1.0
+
+ movprfx z0, z1
+ fcpy z0.s, p0/m, #1.0
+
+ ret