gas/

	* config/tc-mips.c (mips_set_options): Add ase_mcu.
	(mips_opts): Initialise ase_mcu to -1.
	(ISA_SUPPORTS_MCU_ASE): New macro.
	(MIPS_CPU_ASE_MCU): Likewise.
	(is_opcode_valid): Handle MCU.
	(macro_build, macro): Likewise.
	(validate_mips_insn, validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_MCU and OPTION_NO_MCU.
	(md_longopts): Add mmcu and mno-mcu.
	(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
	(mips_after_parse_args): Handle MCU.
	(s_mipsset): Likewise.
	(md_show_usage): Handle MCU options.

	* doc/as.texinfo: Document -mmcu and -mno-mcu options.
	* doc/c-mips.texi: Likewise, and document ".set mcu" and
	".set nomcu" directives.

	gas/testsuite/
	* gas/mips/micromips@mcu.d: New test.
	* gas/mips/mcu.d: Likewise.
	* gas/mips/mcu.s: New test source.
	* gas/mips/mips.exp: Run the new tests.

	include/opcode/
	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
	(INSN_ASE_MASK): Add the MCU bit.
	(INSN_MCU): New macro.
	(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.

	opcodes/
	* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
	and "mips64r2".
	(print_insn_args, print_insn_micromips): Handle MCU.
	* micromips-opc.c (MC): New macro.
	(micromips_opcodes): Add "aclr", "aset" and "iret".
	* mips-opc.c (MC): New macro.
	(mips_builtin_opcodes): Add "aclr", "aset" and "iret".

5 files changed, 325 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5e81c90..4526e2f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,12 @@
 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
+            Chao-ying Fu  <fu@mips.com>
+
+	* gas/mips/micromips@mcu.d: New test.
+	* gas/mips/mcu.d: Likewise.
+	* gas/mips/mcu.s: New test source.
+	* gas/mips/mips.exp: Run the new tests.
+
+2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* gas/mips/micromips.d: Update according to changes to enable
 	microMIPS branch swapping.
diff --git a/gas/testsuite/gas/mips/mcu.d b/gas/testsuite/gas/mips/mcu.d
new file mode 100644
index 0000000..06e5bae
--- /dev/null
+++ b/gas/testsuite/gas/mips/mcu.d
@@ -0,0 +1,122 @@
+#objdump: -dr --show-raw-insn
+#name: MCU for MIPS32r2
+#as: -32
+#source: mcu.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+[ 0-9a-f]+:	42000038 	iret
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04071000 	aclr	0x1,0\(zero\)
+[ 0-9a-f]+:	04072000 	aclr	0x2,0\(zero\)
+[ 0-9a-f]+:	04073000 	aclr	0x3,0\(zero\)
+[ 0-9a-f]+:	04074000 	aclr	0x4,0\(zero\)
+[ 0-9a-f]+:	04075000 	aclr	0x5,0\(zero\)
+[ 0-9a-f]+:	04076000 	aclr	0x6,0\(zero\)
+[ 0-9a-f]+:	04077000 	aclr	0x7,0\(zero\)
+[ 0-9a-f]+:	04477000 	aclr	0x7,0\(v0\)
+[ 0-9a-f]+:	07e77000 	aclr	0x7,0\(ra\)
+[ 0-9a-f]+:	07e777ff 	aclr	0x7,2047\(ra\)
+[ 0-9a-f]+:	07e77800 	aclr	0x7,-2048\(ra\)
+[ 0-9a-f]+:	24011000 	li	at,4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277800 	aclr	0x7,-2048\(at\)
+[ 0-9a-f]+:	2401f000 	li	at,-4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	042777ff 	aclr	0x7,2047\(at\)
+[ 0-9a-f]+:	34018000 	li	at,0x8000
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277fff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277fff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	3c01f000 	lui	at,0xf000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	04877fff 	aclr	0x7,-1\(a0\)
+[ 0-9a-f]+:	3c011234 	lui	at,0x1234
+[ 0-9a-f]+:	34215000 	ori	at,at,0x5000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277678 	aclr	0x7,1656\(at\)
+[ 0-9a-f]+:	24610000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	foo
+[ 0-9a-f]+:	04271000 	aclr	0x1,0\(at\)
+[ 0-9a-f]+:	24610000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	foo
+[ 0-9a-f]+:	04279000 	aset	0x1,0\(at\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04079000 	aset	0x1,0\(zero\)
+[ 0-9a-f]+:	0407a000 	aset	0x2,0\(zero\)
+[ 0-9a-f]+:	0407b000 	aset	0x3,0\(zero\)
+[ 0-9a-f]+:	0407c000 	aset	0x4,0\(zero\)
+[ 0-9a-f]+:	0407d000 	aset	0x5,0\(zero\)
+[ 0-9a-f]+:	0407e000 	aset	0x6,0\(zero\)
+[ 0-9a-f]+:	0407f000 	aset	0x7,0\(zero\)
+[ 0-9a-f]+:	0447f000 	aset	0x7,0\(v0\)
+[ 0-9a-f]+:	07e7f000 	aset	0x7,0\(ra\)
+[ 0-9a-f]+:	07e7f7ff 	aset	0x7,2047\(ra\)
+[ 0-9a-f]+:	07e7f800 	aset	0x7,-2048\(ra\)
+[ 0-9a-f]+:	24011000 	li	at,4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f800 	aset	0x7,-2048\(at\)
+[ 0-9a-f]+:	2401f000 	li	at,-4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f7ff 	aset	0x7,2047\(at\)
+[ 0-9a-f]+:	34018000 	li	at,0x8000
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427ffff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427ffff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	3c01f000 	lui	at,0xf000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	0487ffff 	aset	0x7,-1\(a0\)
+[ 0-9a-f]+:	3c011234 	lui	at,0x1234
+[ 0-9a-f]+:	34215000 	ori	at,at,0x5000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f678 	aset	0x7,1656\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mcu.s b/gas/testsuite/gas/mips/mcu.s
new file mode 100644
index 0000000..182008a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mcu.s
@@ -0,0 +1,70 @@
+	.text
+	.set	mcu
+	.ent	foo
+	.globl	foo
+foo:
+	iret
+
+	aclr	0, 0
+	aclr	0, ($0)
+	aclr	0, 0($0)
+	aclr	1, 0($0)
+	aclr	2, 0($0)
+	aclr	3, 0($0)
+	aclr	4, 0($0)
+	aclr	5, 0($0)
+	aclr	6, 0($0)
+	aclr	7, 0($0)
+	aclr	7, 0($2)
+	aclr	7, 0($31)
+	aclr	7, 2047($31)
+	aclr	7, -2048($31)
+	aclr	7, 2048($31)
+	aclr	7, -2049($31)
+	aclr	7, 32767($31)
+	aclr	7, -32768($31)
+	aclr	7, 65535($4)
+	aclr	7, 65536($4)
+	aclr	7, 0xffff0000($4)
+	aclr	7, 0xffff8000($4)
+	aclr	7, 0xffff0001($4)
+	aclr	7, 0xffff8001($4)
+	aclr	7, 0xf0000000($4)
+	aclr	7, 0xffffffff($4)
+	aclr	7, 0x12345678($4)
+
+	aclr	1, %lo(foo)($3)
+	aset	1, %lo(foo)($3)
+
+	aset	0, 0
+	aset	0, ($0)
+	aset	0, 0($0)
+	aset	1, 0($0)
+	aset	2, 0($0)
+	aset	3, 0($0)
+	aset	4, 0($0)
+	aset	5, 0($0)
+	aset	6, 0($0)
+	aset	7, 0($0)
+	aset	7, 0($2)
+	aset	7, 0($31)
+	aset	7, 2047($31)
+	aset	7, -2048($31)
+	aset	7, 2048($31)
+	aset	7, -2049($31)
+	aset	7, 32767($31)
+	aset	7, -32768($31)
+	aset	7, 65535($4)
+	aset	7, 65536($4)
+	aset	7, 0xffff0000($4)
+	aset	7, 0xffff8000($4)
+	aset	7, 0xffff0001($4)
+	aset	7, 0xffff8001($4)
+	aset	7, 0xf0000000($4)
+	aset	7, 0xffffffff($4)
+	aset	7, 0x12345678($4)
+	.end	foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space	8
diff --git a/gas/testsuite/gas/mips/micromips@mcu.d b/gas/testsuite/gas/mips/micromips@mcu.d
new file mode 100644
index 0000000..eec0ed7
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@mcu.d
@@ -0,0 +1,122 @@
+#objdump: -dr --show-raw-insn
+#name: MCU for MIPS32r2
+#as: -32
+#source: mcu.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+[ 0-9a-f]+:	0000 d37c 	iret
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2020 b000 	aclr	0x1,0\(zero\)
+[ 0-9a-f]+:	2040 b000 	aclr	0x2,0\(zero\)
+[ 0-9a-f]+:	2060 b000 	aclr	0x3,0\(zero\)
+[ 0-9a-f]+:	2080 b000 	aclr	0x4,0\(zero\)
+[ 0-9a-f]+:	20a0 b000 	aclr	0x5,0\(zero\)
+[ 0-9a-f]+:	20c0 b000 	aclr	0x6,0\(zero\)
+[ 0-9a-f]+:	20e0 b000 	aclr	0x7,0\(zero\)
+[ 0-9a-f]+:	20e2 b000 	aclr	0x7,0\(v0\)
+[ 0-9a-f]+:	20ff b000 	aclr	0x7,0\(ra\)
+[ 0-9a-f]+:	20ff b7ff 	aclr	0x7,2047\(ra\)
+[ 0-9a-f]+:	20ff b800 	aclr	0x7,-2048\(ra\)
+[ 0-9a-f]+:	3020 1000 	li	at,4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b800 	aclr	0x7,-2048\(at\)
+[ 0-9a-f]+:	3020 f000 	li	at,-4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b7ff 	aclr	0x7,2047\(at\)
+[ 0-9a-f]+:	5020 8000 	li	at,0x8000
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 bfff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 bfff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	41a1 f000 	lui	at,0xf000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	20e4 bfff 	aclr	0x7,-1\(a0\)
+[ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
+[ 0-9a-f]+:	5021 5000 	ori	at,at,0x5000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b678 	aclr	0x7,1656\(at\)
+[ 0-9a-f]+:	3023 0000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	foo
+[ 0-9a-f]+:	2021 b000 	aclr	0x1,0\(at\)
+[ 0-9a-f]+:	3023 0000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	foo
+[ 0-9a-f]+:	2021 3000 	aset	0x1,0\(at\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2020 3000 	aset	0x1,0\(zero\)
+[ 0-9a-f]+:	2040 3000 	aset	0x2,0\(zero\)
+[ 0-9a-f]+:	2060 3000 	aset	0x3,0\(zero\)
+[ 0-9a-f]+:	2080 3000 	aset	0x4,0\(zero\)
+[ 0-9a-f]+:	20a0 3000 	aset	0x5,0\(zero\)
+[ 0-9a-f]+:	20c0 3000 	aset	0x6,0\(zero\)
+[ 0-9a-f]+:	20e0 3000 	aset	0x7,0\(zero\)
+[ 0-9a-f]+:	20e2 3000 	aset	0x7,0\(v0\)
+[ 0-9a-f]+:	20ff 3000 	aset	0x7,0\(ra\)
+[ 0-9a-f]+:	20ff 37ff 	aset	0x7,2047\(ra\)
+[ 0-9a-f]+:	20ff 3800 	aset	0x7,-2048\(ra\)
+[ 0-9a-f]+:	3020 1000 	li	at,4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3800 	aset	0x7,-2048\(at\)
+[ 0-9a-f]+:	3020 f000 	li	at,-4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 37ff 	aset	0x7,2047\(at\)
+[ 0-9a-f]+:	5020 8000 	li	at,0x8000
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3fff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3fff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	41a1 f000 	lui	at,0xf000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	20e4 3fff 	aset	0x7,-1\(a0\)
+[ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
+[ 0-9a-f]+:	5021 5000 	ori	at,at,0x5000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3678 	aset	0x7,1656\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a66c711..63c2666 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1053,4 +1053,7 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "micromips-branch-relax-pic"
 	run_dump_test "micromips-branch-delay"
     }
+
+    run_dump_test_arches "mcu"		[mips_arch_list_matching mips32r2 \
+					    !octeon]
 }