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author | Richard Earnshaw <richard.earnshaw@arm.com> | 2002-01-18 17:01:55 +0000 |
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committer | Richard Earnshaw <richard.earnshaw@arm.com> | 2002-01-18 17:01:55 +0000 |
commit | 03b1477f5d6d5d385a4b080d7fcd7c15e9e98556 (patch) | |
tree | 580ef898c04429946bf158d03ac9c34ec3e71f04 /gas/doc | |
parent | 2a538ba50cdd625e18a08052a2d326d19b5c63bd (diff) | |
download | fsf-binutils-gdb-03b1477f5d6d5d385a4b080d7fcd7c15e9e98556.zip fsf-binutils-gdb-03b1477f5d6d5d385a4b080d7fcd7c15e9e98556.tar.gz fsf-binutils-gdb-03b1477f5d6d5d385a4b080d7fcd7c15e9e98556.tar.bz2 |
* NEWS: Mention new ARM command-line options and VFP support.
* config/tc-arm.c (ARM_CEXT_XSCALE): Replaces ARM_EXT_XSCALE. All
uses changed.
(ARM_CEXT_MAVERICK): Similarly.
(ARM_ANY): Now means any core instruction.
(CPU_DEFAULT): Default to ARM_ANY.
(uses_apcs_26, atcps, support_interwork, uses_apcs_float)
(pic_code): Declare for all object types. Make type int.
(legacy_cpu, legacy_fpu, mcpu_cpu_opt, mcpu_fpu_opt, march_cpu_opt)
(march_fpu_opt, mfpu_opt): Declare.
(md_longopts): Tidy up conditional definitions.
(arm_opts, arm_cpus, arm_archs, arm_fpus, arm_extensions)
(arm_long_opts): New tables.
(arm_parse_cpu, arm_parse_arch, arm_parse_fpu): New functions.
(arm_parse_extension): New function.
(md_parse_option): Rewrite using new table-driven system.
(md_show_usage): Use new table-driven system.
(md_begin): Calculate cpu_variant from command line option data.
* doc/as.texinfo (ARM ISA options): Docuement new ARM-specific
command-line options.
* doc/c-arm.texi: Likewise.
Testsuite:
* gas/arm/vfp1.d: Use new command-line options.
* gas/arm/vfp1xD.d: Likewise.
* gas/arm/arm.exp (vfp-bad): Likewise.
* gas/arm/maverick.d: Likewise.
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/as.texinfo | 27 | ||||
-rw-r--r-- | gas/doc/c-arm.texi | 166 |
2 files changed, 144 insertions, 49 deletions
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index fb0fa82..e57bd92 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -274,18 +274,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @ifset ARM @emph{Target ARM options:} - [@b{-m[arm]1}|@b{-m[arm]2}|@b{-m[arm]250}|@b{-m[arm]3}| - @b{-m[arm]6}|@b{-m[arm]60}|@b{-m[arm]600}|@b{-m[arm]610}| - @b{-m[arm]620}|@b{-m[arm]7[t][[d]m[i]][fe]}|@b{-m[arm]70}| - @b{-m[arm]700}|@b{-m[arm]710[c]}|@b{-m[arm]7100}| - @b{-m[arm]7500}|@b{-m[arm]8}|@b{-m[arm]810}|@b{-m[arm]9}| - @b{-m[arm]920}|@b{-m[arm]920t}|@b{-m[arm]9tdmi}| - @b{-mstrongarm}|@b{-mstrongarm110}|@b{-mstrongarm1100}] - [@b{-m[arm]v2}|@b{-m[arm]v2a}|@b{-m[arm]v3}|@b{-m[arm]v3m}| - @b{-m[arm]v4}|@b{-m[arm]v4t}|@b{-m[arm]v5}|@b{-[arm]v5t}| - @b{-[arm]v5te}] - [@b{-mthumb}|@b{-mall}] - [@b{-mfpa10}|@b{-mfpa11}|@b{-mfpe-old}|@b{-mno-fpu}] +@c Don't document the deprecated options + [@b{-mcpu}=@var{processor}[+@var{extension}@dots]] + [@b{-march}=@var{architecture}[+@var{extension}@dots]] + [@b{-mfpu}=@var{floating-point-fromat}] + [@b{-mthumb}] [@b{-EB}|@b{-EL}] [@b{-mapcs-32}|@b{-mapcs-26}|@b{-mapcs-float}| @b{-mapcs-reentrant}] @@ -568,14 +561,14 @@ The following options are available when @value{AS} is configured for the ARM processor family. @table @gcctabopt -@item -m[arm][1|2|3|6|7|8|9][...] +@item -mcpu=@var{processor}[+@var{extension}@dots] Specify which ARM processor variant is the target. -@item -m[arm]v[2|2a|3|3m|4|4t|5|5t] +@item -march=@var{architecture}[+@var{extension}@dots] Specify which ARM architecture variant is used by the target. -@item -mthumb | -mall -Enable or disable Thumb only instruction decoding. -@item -mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu +@item -mfpu=@var{floating-point-format} Select which Floating Point architecture is the target. +@item -mthumb +Enable Thumb only instruction decoding. @item -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi Select which procedure calling convention is in use. @item -EB | -EL diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 450d4f5..5f1b73c 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -31,45 +31,147 @@ @table @code -@cindex @code{-marm} command line option, ARM -@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]} -@itemx -mxscale -@itemx -marm9e +@cindex @code{-mcpu=} command line option, ARM +@item -mcpu=@var{processor}[+@var{extension}@dots] This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which -will not execute on the target processor. - -The option @code{-marm9e} specifies that the target processor is the -Cirrus ARM processor with the Maverick DSP co-processor. - -@cindex @code{-marmv} command line option, ARM -@item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]} +will not execute on the target processor. The following processor names are +recognized: +@code{arm1}, +@code{arm2}, +@code{arm250}, +@code{arm3}, +@code{arm6}, +@code{arm60}, +@code{arm600}, +@code{arm610}, +@code{arm620}, +@code{arm7}, +@code{arm7m}, +@code{arm7d}, +@code{arm7dm}, +@code{arm7di}, +@code{arm7dmi}, +@code{arm70}, +@code{arm700}, +@code{arm700i}, +@code{arm710}, +@code{arm710t}, +@code{arm720}, +@code{arm720t}, +@code{arm740t}, +@code{arm710c}, +@code{arm7100}, +@code{arm7500}, +@code{arm7500fe}, +@code{arm7t}, +@code{arm7tdmi}, +@code{arm8}, +@code{arm810}, +@code{strongarm}, +@code{strongarm1}, +@code{strongarm110}, +@code{strongarm1100}, +@code{strongarm1110}, +@code{arm9}, +@code{arm920}, +@code{arm920t}, +@code{arm922t}, +@code{arm940t}, +@code{arm9tdmi}, +@code{arm9e}, +@code{arm946e-r0}, +@code{arm946e}, +@code{arm966e-r0}, +@code{arm966e}, +@code{arm10t}, +@code{arm10e}, +@code{arm1020}, +@code{arm1020t}, +@code{arm1020e}, +@code{ep9312} (ARM920 with Cirrus Maverick coprocessor), +@code{i80200} (Intel XScale processor) +and +@code{xscale}. +The special name @code{all} may be used to allow the +assembler to accept instructions valid for any ARM processor. + +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics that extend the processor using the +co-processor instruction space. For example, @code{-mcpu=arm920+maverick} +is equivalent to specifying @code{-mcpu=ep9312}. The following extensions +are currently supported: +@code{+maverick} +and +@code{+xscale}. + +@cindex @code{-march=} command line option, ARM +@item -march=@var{architecture}[+@var{extension}@dots] This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which -will not execute on the target architecture. -The option @code{-marmv5te} specifies that v5t architecture should be -used with the El Segundo extensions enabled. +will not execute on the target architecture. The following architecture +names are recognized: +@code{armv1}, +@code{armv2}, +@code{armv2a}, +@code{armv2s}, +@code{armv3}, +@code{armv3m}, +@code{armv4}, +@code{armv4xm}, +@code{armv4t}, +@code{armv4txm}, +@code{armv5}, +@code{armv5t}, +@code{armv5txm}, +@code{armv5te}, +@code{armv5texp} +and +@code{xscale}. +If both @code{-mcpu} and +@code{-march} are specified, the assembler will use +the setting for @code{-mcpu}. + +The architecture option can be extended with the same instruction set +extension options as the @code{-mcpu} option. + +@cindex @code{-mfpu=} command line option, ARM +@item -mfpu=@var{floating-point-format} + +This option specifies the floating point format to assemble for. The +assembler will issue an error message if an attempt is made to assemble +an instruction which will not execute on the target floating point unit. +The following format options are recognized: +@code{softfpa}, +@code{fpe}, +@code{fpa}, +@code{fpa10}, +@code{fpa11}, +@code{arm7500fe}, +@code{softvfp}, +@code{softvfp+vfp}, +@code{vfp}, +@code{vfp10}, +@code{vfp10-r0}, +@code{vfp9}, +@code{vfpxd}, +@code{arm1020t} +and +@code{arm1020e}. + +In addition to determining which instructions are assembled, this option +also affects the way in which the @code{.double} assembler directive behaves +when assembling little-endian code. + +The default is dependent on the processor selected. For Architecture 5 or +later, the default is to assembler for VFP instructions; for earlier +architectures the default is to assemble for FPA instructions. @cindex @code{-mthumb} command line option, ARM @item -mthumb -This option specifies that only Thumb instructions should be assembled. - -@cindex @code{-mall} command line option, ARM -@item -mall -This option specifies that any Arm or Thumb instruction should be assembled. - -@cindex @code{-mfpa} command line option, ARM -@item -mfpa @code{[10|11]} -This option specifies the floating point architecture in use on the -target processor. - -@cindex @code{-mfpe-old} command line option, ARM -@item -mfpe-old -Do not allow the assembly of floating point multiple instructions. - -@cindex @code{-mno-fpu} command line option, ARM -@item -mno-fpu -Do not allow the assembly of any floating point instructions. +This option specifies that the assembler should start assembling Thumb +instructions; that is, it should behave as though the file starts with a +@code{.code 16} directive. @cindex @code{-mthumb-interwork} command line option, ARM @item -mthumb-interwork |