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| author | Walter Lee <walt@tilera.com> | 2012-02-25 19:51:34 +0000 |
|---|---|---|
| committer | Walter Lee <walt@tilera.com> | 2012-02-25 19:51:34 +0000 |
| commit | fb6ceddedd56805fc4fd64792a0e73baa8c22a21 (patch) | |
| tree | 035d5e8c3f9a3be2c2b82f975fcde4e4074ba612 /gas/doc | |
| parent | 825902491e89db303b036d82eef32ef0b07d4317 (diff) | |
| download | fsf-binutils-gdb-fb6ceddedd56805fc4fd64792a0e73baa8c22a21.zip fsf-binutils-gdb-fb6ceddedd56805fc4fd64792a0e73baa8c22a21.tar.gz fsf-binutils-gdb-fb6ceddedd56805fc4fd64792a0e73baa8c22a21.tar.bz2 | |
Add big-endian support for tilegx.
bfd/
* config.bfd (tilegx-*-*): rename little endian vector; add big
endian vector.
(tilegxbe-*-*): New case.
* configure.in (bfd_elf32_tilegx_vec): Rename...
(bfd_elf32_tilegx_le_vec): ... to this.
(bfd_elf32_tilegx_be_vec): New vector.
(bfd_elf64_tilegx_vec): Rename...
(bfd_elf64_tilegx_le_vec): ... to this.
(bfd_elf64_tilegx_be_vec): New vector.
* configure: Regenerate.
* elf32-tilegx.c (TARGET_LITTLE_SYM): Rename.
(TARGET_LITTLE_NAME): Ditto.
(TARGET_BIG_SYM): Define.
(TARGET_BIG_NAME): Define.
* elf64-tilegx.c (TARGET_LITTLE_SYM): Rename.
(TARGET_LITTLE_NAME): Ditto.
(TARGET_BIG_SYM): Define.
(TARGET_BIG_NAME): Define.
* targets.c (bfd_elf32_tilegx_vec): Rename...
(bfd_elf32_tilegx_le_vec): ... to this.
(bfd_elf32_tilegx_be_vec): Declare.
(bfd_elf64_tilegx_vec): Rename...
(bfd_elf64_tilegx_le_vec): ... to this.
(bfd_elf64_tilegx_be_vec): Declare.
(_bfd_target_vector): Add / rename above vectors.
binutils/testsuite/
* binutils-all/objdump.exp (cpus_expected): Add tilegx.
gas/
* tc-tilegx.c (tilegx_target_format): Handle big endian.
(OPTION_EB): Define.
(OPTION_EL): Define.
(md_longopts): Add entries for "EB" and "EL".
(md_parse_option): Handle OPTION_EB and OPTION_EL.
(md_show_usage): Add -EB and -EL.
(md_number_to_chars): New.
* tc-tilegx.h (TARGET_BYTES_BIG_ENDIAN): Guard definition with
ifndef.
(md_number_to_chars): Delete.
* configure.tgt (tilegx*be): Handle.
* doc/as.texinfo [TILE-Gx]: Document -EB and -EL.
* doc/c-tilegx.texi: Ditto.
ld/
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx_be.c.
(ALL_64_EMULATION_SOURCES): Add eelf64tilegx_be.c.
(eelf32tilegx_be.c): Add rule to build this file.
(eelf64tilegx_be.c): Ditto.
* Makefile.in: Regenerate.
* configure.tgt (tilegx-*-*): Support big endian.
(tilegxbe-*-*): New.
* emulparams/elf32tilegx.sh (OUTPUT_FORMAT): Rename.
(BIG_OUTPUT_FORMAT): Define.
(LITTLE_OUTPUT_FORMAT): Define.
* emulparams/elf32tilegx_be.sh: New.
* emulparams/elf64tilegx.sh (OUTPUT_FORMAT): Rename.
(BIG_OUTPUT_FORMAT): Define.
(LITTLE_OUTPUT_FORMAT): Define.
* emulparams/elf64tilegx_be.sh: New.
ld/testsuite/
* ld-tilegx/reloc-be.d: New.
* ld-tilegx/reloc-le.d: New.
* ld-tilegx/reloc.d: Delete.
* ld-tilegx/tilegx.exp: Test big and little endian.
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/as.texinfo | 2 | ||||
| -rw-r--r-- | gas/doc/c-tilegx.texi | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 7a41f02..81ad370 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -497,7 +497,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @ifset TILEGX @emph{Target TILE-Gx options:} - [@b{-m32}|@b{-m64}] + [@b{-m32}|@b{-m64}][@b{-EB}][@b{-EL}] @end ifset @ifset TILEPRO @c TILEPro has no machine-dependent assembler options diff --git a/gas/doc/c-tilegx.texi b/gas/doc/c-tilegx.texi index 66dd5a3..c2f5bc1 100644 --- a/gas/doc/c-tilegx.texi +++ b/gas/doc/c-tilegx.texi @@ -33,6 +33,11 @@ The following table lists all available TILE-Gx specific options: @item -m32 | -m64 Select the word size, either 32 bits or 64 bits. +@cindex @samp{-EB} option, TILE-Gx +@cindex @samp{-EL} option, TILE-Gx +@item -EB | -EL +Select the endianness, either big-endian (-EB) or little-endian (-EL). + @end table @c man end |