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| author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2018-01-15 14:11:02 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2018-01-15 14:11:02 +0000 |
| commit | 2875ce2b55bdda40107ef3500edfeccfb29f14e6 (patch) | |
| tree | ae0b35dfd39a8605accf6b3d0bcf2e11e7aed654 /gas/config | |
| parent | df9909b8675c8c9b6fa88c5d13afd2efa66dcf68 (diff) | |
| download | fsf-binutils-gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.zip fsf-binutils-gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.tar.gz fsf-binutils-gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.tar.bz2 | |
[ARM] Enable conditional Armv8-M instructions
Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index c07362a..925d994 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -21456,20 +21456,20 @@ static const struct asm_opcode insns[] = #define ARM_VARIANT NULL #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8m - TUE("sg", 0, e97fe97f, 0, (), 0, noargs), - TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx), - TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx), - TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt), - TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt), - TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt), - TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt), + TUE("sg", 0, e97fe97f, 0, (), 0, noargs), + TCE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx), + TCE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx), + TCE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt), + TCE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt), + TCE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt), + TCE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt), /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the instructions behave as nop if no VFP is present. */ #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8m_main - TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn), - TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn), + TCE("vlldm", 0, ec300a00, 1, (RRnpc), 0, rn), + TCE("vlstm", 0, ec200a00, 1, (RRnpc), 0, rn), }; #undef ARM_VARIANT #undef THUMB_VARIANT |