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| author | H.J. Lu <hjl.tools@gmail.com> | 2019-03-18 03:50:45 +0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2019-03-18 03:51:50 +0800 |
| commit | 99112332cda2e63d33959ac8ea2ed13524b09bd6 (patch) | |
| tree | 5dc762d698d2a2b62d4552a505516c7b91b78b76 /gas/config | |
| parent | d4cbef22ba406707a4fcb30a7a57308447626f14 (diff) | |
| download | fsf-binutils-gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.zip fsf-binutils-gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.tar.gz fsf-binutils-gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.tar.bz2 | |
x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 8047ddf..856c18d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3977,8 +3977,7 @@ optimize_encoding (void) } } } - else if (optimize > 1 - && i.reg_operands == 3 + else if (i.reg_operands == 3 && i.op[0].regs == i.op[1].regs && !i.types[2].bitfield.xmmword && (i.tm.opcode_modifier.vex @@ -4009,15 +4008,15 @@ optimize_encoding (void) || i.tm.base_opcode == 0x6647) && i.tm.extension_opcode == None)) { - /* Optimize: -O2: + /* Optimize: -O1: VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, vpsubq and vpsubw: EVEX VOP %zmmM, %zmmM, %zmmN -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) EVEX VOP %ymmM, %ymmM, %ymmN -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) VEX VOP %ymmM, %ymmM, %ymmN -> VEX VOP %xmmM, %xmmM, %xmmN VOP, one of vpandn and vpxor: @@ -4026,17 +4025,17 @@ optimize_encoding (void) VOP, one of vpandnd and vpandnq: EVEX VOP %zmmM, %zmmM, %zmmN -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) EVEX VOP %ymmM, %ymmM, %ymmN -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) VOP, one of vpxord and vpxorq: EVEX VOP %zmmM, %zmmM, %zmmN -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) EVEX VOP %ymmM, %ymmM, %ymmN -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) - -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) + -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) VOP, one of kxord and kxorq: VEX VOP %kM, %kM, %kN -> VEX kxorw %kM, %kM, %kN @@ -4054,8 +4053,9 @@ optimize_encoding (void) i.tm.opcode_modifier.vexw = VEXW0; i.tm.opcode_modifier.evex = 0; } - else if (cpu_arch_flags.bitfield.cpuavx512vl - || cpu_arch_isa_flags.bitfield.cpuavx512vl) + else if (optimize > 1 + && (cpu_arch_flags.bitfield.cpuavx512vl + || cpu_arch_isa_flags.bitfield.cpuavx512vl)) i.tm.opcode_modifier.evex = EVEX128; else return; |