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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:46:54 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:31:34 +0100 |
| commit | 1889da7048b310151d142b100678b6bd6053b548 (patch) | |
| tree | e0e8d1d48cd6814f4c10ea01da58235a3c81728b /gas/config | |
| parent | 65d1bc05e89e45b102783422c3984ed718547d5c (diff) | |
| download | fsf-binutils-gdb-1889da7048b310151d142b100678b6bd6053b548.zip fsf-binutils-gdb-1889da7048b310151d142b100678b6bd6053b548.tar.gz fsf-binutils-gdb-1889da7048b310151d142b100678b6bd6053b548.tar.bz2 | |
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 5643e3f..5d7f2c0 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -22946,6 +22946,7 @@ md_pcrel_from_section (fixS * fixP, segT seg) case BFD_RELOC_THUMB_PCREL_BRANCH25: case BFD_RELOC_ARM_THUMB_BF17: case BFD_RELOC_ARM_THUMB_BF19: + case BFD_RELOC_ARM_THUMB_BF13: return base + 4; case BFD_RELOC_THUMB_PCREL_BRANCH23: @@ -24909,6 +24910,39 @@ md_apply_fix (fixS * fixP, } break; + case BFD_RELOC_ARM_THUMB_BF13: + if (fixP->fx_addsy + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) + { + /* Force a relocation for a branch 13 bits wide. */ + fixP->fx_done = 0; + } + + if (v8_1_branch_value_check (value, 13, TRUE) == FAIL) + as_bad_where (fixP->fx_file, fixP->fx_line, + BAD_BRANCH_OFF); + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT immA, immB, immC; + + immA = (value & 0x00001000) >> 12; + immB = (value & 0x00000ffc) >> 2; + immC = (value & 0x00000002) >> 1; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= immA; + newval2 |= (immC << 11) | (immB << 1); + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; + case BFD_RELOC_ARM_V4BX: /* This will need to go in the object file. */ fixP->fx_done = 0; @@ -25093,6 +25127,7 @@ tc_gen_reloc (asection *section, fixS *fixp) case BFD_RELOC_ARM_FUNCDESC: case BFD_RELOC_ARM_THUMB_BF17: case BFD_RELOC_ARM_THUMB_BF19: + case BFD_RELOC_ARM_THUMB_BF13: code = fixp->fx_r_type; break; |